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FINAL
AM79C30A/32A
Digital Subscriber ControllerTM (DSCTM) Circuit
DISTINCTIVE CHARACTERISTICS
s Combines CCITT I.430 S/T-Interface Transceiver, D-Channel LAPD Processor, Audio s Processor (DSC device only), and IOM-2 Interface in a single chip s Special operating modes allow realization of CCITT I.430 power-compliant terminal equipment s S- or T-Interface Transceiver -- Level 1 Physical Layer Controller -- Supports point-to-point, short and extended passive bus configurations -- Provides multiframe support s Certified protocol software support available s CMOS technology, TTL compatible s D-channel processing capability -- Flag generation/detection -- CRC generation/checking -- Zero insertion/deletion -- Four 2-byte address detectors -- 32-byte receive and 16-byte transmit FIFOs
BLOCK DIAGRAM
SBP/IOM-2 Interface CAP1 CAP2 SBIN SCLK BCL/CH2STRB* SBIOUT SFS
HSW
AINA AREF AINB EAR1 EAR2 LS1 LS2
Audio Interface
Main Audio Processor (MAP) (AM79C30A Only)
Peripheral Port (PP)
S/T Line Interface Unit (LIU) D Channel B1
LOUT1 LOUT2 LIN1 LIN2
Bd Be Bf
Ba
B-channel Multiplexer (MUX)
B2 D-Channel Data Link Controller (DLC)
XTAL1 XTAL2 MCLK
Oscillator (OSC) Bb Bc
D Channel CS WR RD Microprocessor Interface (MUX) RESET
D7 D6 D5 D4 D3 D2 D1 D0 INT A2 Microprocessor Interface
A1 A0 09893H-1
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 09893 Rev: H Amendment/0 Issue Date: December 1998
S/T Interface
DISTINCTIVE CHARACTERISTICS (continued)
s Audio processing capability (DSC circuit only) -- Registers for implementation of software-based speaker phone algorithms -- Dual audio inputs -- Earpiece and loudspeaker drivers -- Codec/filter with A/ selection -- Programmable gain and equalization filters -- Programmable sidetone level -- Programmable DTMF, single tone, progress tone, and ringer tone generation -- Programmable on-chip microphone amplifier s Pin and software compatible with the Am79C32A ISDN Data Controller (IDCTM) Circuit. The Am79C32A is used in data-only applications.
GENERAL DESCRIPTION
The AM79C30A Digital Subscriber Controller (DSC) Circuit and Am79C32A ISDN Data Controller (IDC) Circuit, shown in the Block Diagram, allow the realization of highly-integrated Terminal Equipment for the ISDN. The AM79C30A/32A is fully compatible with the CCITT-I-series recommendations for the S and T reference points, ensuring that the user of the device may design TEs which conform to the international standards. The AM79C30A/32A provides a 192-Kbit/s full duplex digital path over four wires between the TE located on the subscriber's premises and the NT or PABX linecard. All physical layer functions and procedures are implemented in accordance with CCITT Recommendation I.430, including framing, synchronization, maintenance, and multiple ter minal contention. Both point-to-point and point-to-multipoint configurations are supported. The AM79C30A/32A processes the ISDN basic rate bit stream, which consists of B1 (64 Kbit/s), B2 (64 Kbit/s), and D (16 Kbit/s) channels. The B channels are routed to and from different sections of the AM79C30A/32A under software control. The D channel is partially processed by the DSC/IDC circuit and is passed to the microprocessor for further processing. The Main Audio Processor (MAP) uses Digital Signal Processing (DSP) to implement a high performance codec/filter function. The MAP interface supports a loudspeaker, an earpiece, and two separate audio inputs. Programmable on-chip gain is provided to simplify use of low output level microphones. The user may alter frequency response and gain of the MAP receive and transmit paths. Tone generators are included to implement ringing, call progress, and DTMF signals. A Peripheral Port (PP) is provided to allow the B channels to be routed off-chip for processing by other peripherals. This por t is configurable as either an industry-standard IOM-2 port, or as a serial bus port (SBP). The TE design process is simplified by the availability of certified protocol software packages, which provide complete system solutions through OSI Layer 3.
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AM79C30A/32A Data Sheet
CONNECTION DIAGRAMS Top View
44-Pin PLCC AREF EAR2 EAR1 AINB AINA AVSS HSW 40 39 38 37 36 35 AM79C30A 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 LIN1 42 LIN2 41 LS2 LS1 44
CAP1 CAP2 AVCC DV CC RESET CS RD WR DV SS A2 A1
7 8 9 10 11 12 13 14 15 16 17
43
6
5
4
3
2
1
LOUT1 LOUT2 AVSS DV SS INT XTAL1 XTAL2 MCLK SFS SCLK SBOUT
BCL/CH2STRB
44-Pin PLCC RSRVD RSRVD RSRVD RSRVD RSRVD AREF HSW 40 39 38 37 36 35 Am79C32A 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 LIN1 42 LIN2 41 LS2 LS1
44
RSRVD RSRVD AVCC DV CC RESET CS RD WR DV SS A2 A1
7 8 9 10 11 12 13 14 15 16 17
43
6
5
4
3
2
1
SBIN
A0
D7
D6
D5
D4
D3
D2
D1
D0
LOUT1 LOUT2 AVSS DV SS INT XTAL1 XTAL2 MCLK SFS SCLK SBOUT
BCL/CH2STRB
Note: 1. Pin 1 is marked for orientation purposes.
2. RSRVD = Reserved pin; should not be connected externally to any signal or supply.
AM79C30A/32A Data Sheet
SBIN
A0
D7
D6
D5
D4
D3
D2
D1
D0
3
CONNECTION DIAGRAMS (continued) Top View
44-Pin TQFP AREF EAR2 EAR1 AINB AINA AVSS HSW 34 LIN1 36 LIN2 35 LS2 39 LS1 38
44
43
42
41
40
CAP1 CAP2 AVCC DV CC RESET CS RD WR DV SS A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 AM79C30A
37
33 32 31 30 29 28 27 26 25 24 23
LOUT1 LOUT2 AVSS DVSS INT XTAL1 XTAL2 MCLK SFS SCLK SBOUT
BCL/CH2STRB
44-Pin TQFP RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD HSW 34 33 32 31 30 29 Am79C32A 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 LIN1 36 LIN2 35 LS2 LS1
44
43
42
41
40
39
38
RSRVD RSRVD AVCC DV CC RESET CS RD WR DV SS A2 A1
37
SBIN
A0
D7
D6
D5
D4
D3
D2
D1
D0
1 2 3 4 5 6 7 8 9 10 11
LOUT1 LOUT2 AVSS DVSS INT XTAL1 XTAL2 MCLK SFS SCLK SBOUT
BCL/CH2STRB
Note: Pin 1 is marked for orientation purposes.
4
AM79C30A/32A Data Sheet
SBIN
A0
D7
D6
D5
D4
D3
D2
D1
D0
ORDERING INFORMATION Standard Products
AMD (R) standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
AM79C30A/32A
J
C
OPTIONAL PROCESSING Blank = Standard Processing
TEMPERATURE RANGE C = Commercial (0C to +70C)
PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) V = 44-Pin Thin Plastic Quad Flat Pack (PQT044)
SPEED OPTION Not Applicable DEVICE NAME/DESCRIPTION AM79C30A/32A Digital Subscriber Controller (DSC) device ISDN Data Controller (IDC) device
Valid Combinations AM79C30A AM79C32A JC, VC JC, VC
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Reference Appendix C, Figures 1 & 2, for specific mechanical dimensions of the two packages.
AM79C30A/32A Data Sheet
5
PIN DESCRIPTION* Line Interface Unit (LIU)
HSW Hook-Switch (Input) The HSW signal indicates if the hook-switch is on or off hook. This signal may be generated with a mechanical switch wired to ground with a pull-up resistor to VCC. Any change in the HSW state causes an interrupt. LIN1, LIN2 Subscriber Line Input (Differential Inputs) The LIN1 and LIN2 inputs interface to the subscriber (S reference point) via an isolation transformer. LIN2 is the positive input; LIN1 is the negative input. These pins are not TTL compatible. LOUT1, LOUT2 Subscriber Line Output (Differential Outputs) The LOUT1 and LOUT2 line driver output signals interface to the subscriber line at the S reference point via an isolation transformer and resistors. LOUT2 is the positive S-interface driver (sources current during a High mark), and LOUT1 is the negative S-interface dr iver ( sou rce s cur ren t d ur ing Low ma r k). Fo r multi-point applications, all TEs must maintain the same polarity on the S Interface. These pins are not TTL compatible.
EAR1, EAR2 Earpiece Interface (Differential Outputs) EAR1 and EAR2 are the outputs from the receive path of the codec/filter. These differential outputs can directly drive a minimum load of 130 ohms. LS1, LS2 Loudspeaker Interface (Differential Outputs) LS1 and LS2 are push-pull outputs which can directly drive a minimum load of 40 ohms.
Microprocessor Interface (MPI)
A2-A0 Address Line (Inputs) A2, A1, and A0 signals select source and destination registers for read and write operations on the data bus. CS Chip Select (Input) CS must be Low to read or write to the AM79C30A/ 32A. Data transfer occurs over the bidirectional data lines (D7-D0). D7-D0 Data Bus (Bidirectional with High-Impedance State) The eight bidirectional data bus lines are used to exchange information with the microprocessor. D0 is the least significant bit (LSB) and D7 is the most significant bit (MSB). A High on the data bus line corresponds to a logic 1, and Low corresponds to a logic 0. These lines act as inputs when both WR and CS are active and as outputs when both RD and CS are active. When CS is inactive or both RD and WR are inactive, the D7-D0 pins are in a high-impedance state. INT Interrupt (Output) An active Low output on the INT pin informs the external microprocessor that the AM79C30A/32A needs interrupt service. INT is updated once every 125 s. The INT pin remains active until the Interrupt Register (IR) is read or the AM79C30A/32A is reset. RESET Reset (Input) Reset is an active High signal which causes the AM79C30A/32A to immediately terminate its present activity and initialize to the reset condition. When reset returns Low, the AM79C30A/32A enters the Idle mode. The MCLK output remains active while RESET is held High.
Main Audio Processor (MAP)
All MAP pins are analog, and therefore are not TTL compatible. AINA, AINB Analog (Inputs) These analog inputs allow for two separate analog (audio) inputs to the transmit path of the codec/filter.Input signals on either of these pins must be referenced to AREF. AREF Analog Reference (Output) This is a nominal 2.25-V reference voltage output for biasing the analog inputs. When the MAP is disabled, this pin is high impedance. CAP1, CAP2 Capacitor/Resistor (CAP1, Input; CAP2, Output) An external resistor and capacitor are connected in series between these pins. These components are needed for the integrator in the Analog-to-Digital Converter (ADC).
Note: * All signal levels are TTL compatible unless otherwise stated.
6
AM79C30A/32A Data Sheet
RD Read (Input) The active Low read signal is conditioned by CS and indicates that internal information is to be transferred onto the data bus. A number of internal registers are user accessible. The contents of the accessed register are transferred onto the data bus after the High to Low transition of the RD input. WR Write (Input) The active Low write signal is conditioned by CS and indicates that external information on the data bus is to be transferred to an internal register. The contents of the data bus are loaded on the Low to High transition of the WR input.
Peripheral Port is programmed to IOM-2 mode, SBOUT functions as the data output except in the special case of IOM-2 Slave mode when it becomes an input during part or all of the IOM-2 frame. SCLK Serial Data Clock (Input/Output) When the PP is programmed to SBP mode, SCLK outputs a 192-kHz data clock, which may be inverted under software control. When the PP is programmed to IOM-2 Master mode, SCLK outputs a 1.536-MHz 2X data clock. In IOM-2 Slave mode, SCLK functions as the clock input. The SCLK pin defaults to a high-impedance state upon reset, but becomes active after any MUX connection is made or if the PP is programmed to IOM-2 Master mode. SFS Serial Frame Sync (Input/Output) In SBP mode, SFS outputs an 8-kHz frame synchronization signal. SFS is an output in IOM-2 Master mode, and an input in IOM-2 Slave mode. As an output, SFS is active for 8-bit periods. The SFS pin defaults to a high-impedance state upon reset, but becomes active after any MUX connection is made or if the PP is programmed to IOM-2 Master mode. For SBP mode, the active signal state is Low during Idle and 8 kHz in Active Data Only and Active Voice and Data modes. BCL/CH2STRB Bit Clock/SBP Channel 2 Strobe (Output, Three-state) In SBP mode, this pin provides a strobe during the 8-bit times of the second 64-kbit/s data channel. In IOM-2 Master mode, this pin provides a 768-kHz bit clock to aid in the connection of non-IOM-2 devices to the port. In IOM-2 Slave mode, this pin is high-impedance.
Oscillator (OSC)
MCLK Master Clock (Output) The MCLK output is available for use as the system clock for the microprocessor. MCLK is derived from the 12.288-MHz crystal via a programmable divider in the AM79C30A/32A which provides the following MCLK output frequencies: 12.288, 6.144, 4.096, 3.072, 1.536, 0.768, and 0.384 MHz. XTAL1, XTAL2 External Crystal (Output, Input) XTAL1 and XTAL2 are connected to an external parallel resonant crystal for the on-chip oscillator. XTAL2 can also be connected to an external source instead of a crystal, in which case XTAL1 should be left disconnected. The frequency must be 12.288 MHz, 80 ppm.
Peripheral Port (PP)
SBIN Serial Data (Input/Output) When the Peripheral Port is programmed to SBP mode, SBIN operates as an input for serial data. When the Peripheral Port is programmed to IOM-2 mode, SBIN functions as the data input except in the special case of IOM-2 Slave mode, when it becomes an open-drain output during part or all of the IOM-2 frame, or when deactivated. SBOUT Serial Data (Input/Output) When the Peripheral Port is programmed to SBP mode, SBOUT operates as an output for serial data. When the
Power Supply Pins
PLCC/TQFP Packages AVCC AVSS DVSS DVCC +5-V analog power supply, 5% Analog ground Digital ground +5-V digital power supply, 5%
Note: For best performance, decoupling capacitors should be installed between VCC and VSS as close to the chip as possible. Do not use separate supplies for analog and digital power and ground connections.
AM79C30A/32A Data Sheet
7
OPERATIONAL DESCRIPTION Overview of Power Modes
The minimization of power consumption is a key factor in the design of Terminal Equipment for the ISDN, and the DSC/IDC circuit employs two basic approaches to power management: 1. The power consumption of the DSC/IDC circuit itself is managed by using four basic power modes which allow unused functional blocks to be disabled. The INIT register may be programmed to select Active Voice and Data, Active Data Only, Idle, or Power-Down mode, depending upon which DSC/ IDC device resources are required at the time. 2. The power consumption of the controlling micro-processor system may be controlled by driving the processor clock with the DSC/IDC circuit MCLK output. A wide range of MCLK operating frequencies may be selected, and a special Clock Speed-Up function is provided which increases the speed of MCLK upon the occurrence of a key event, without processor intervention. Control of MCLK frequency and Clock Speed-up is accomplished by programming the INIT and INIT2 registers, as described later.
Idle mode reduces DSC/IDC circuit power consumption by disabling the MUX, DLC, and MAP functional blocks. The Peripheral Port is also disabled, except that an IOM-2 activation request interrupt is possible, and the SFS and SCLK outputs may still be activated. The SFS and SCLK outputs are high impedance upon RESET, but become active after any MUX connection is programmed. The DLC read-only registers are cleared when the DSC/IDC circuit enters the Idle mode.
Power-Down Mode
Power-Down mode consumes the least power of all the DSC/IDC power options, and differs from Idle mode in that all clocks, including the XTAL oscillator, are stopped. Most functional blocks are disabled, except for those required to recognize key external events that will force the DSC/IDC circuit to return to Idle mode. The Power-Down mode is not available unless the Power-Down Enable bit is set in the INIT2 register; see the INIT2 register description for further details. Entering the Power-Down Mode The Power-Down mode is entered by appropriate programming of the INIT and INIT2 registers. Selection of the Power-Down mode causes the DSC/IDCcircuit to begin an internal countdown of at least 250 MCLK cycles after which the MCLK and XTAL1 outputs are both stopped and held High, and the XTAL2input will be disregarded. The purpose of this countdown cycle is to allow the microprocessor time for housekeeping operations before its clock is stopped. If an interrupt causes the DSC INT pin to go Low during the countdown, the Power-Down mode bits in the INIT register will be reset and the countdown will be canceled. If the LIU is enabled and in any state other than F3 at the end of the countdown, MCLK is stopped but the oscillator continues to run. This allows the LIU to identify the incoming signal and either (1) generate an interrupt and force the DSC/IDC circuit to Idle mode when activation is complete, or (2) move to the F3 state and stop the oscillator once the line goes idle. Exiting the Power-Down Mode The DSC/IDC circuit will exit the Power-Down mode and enter the Idle mode if any of the following events occur: * * The DSC/IDC circuit receives a hardware reset via the RESET pin. The CS and WR pins are both pulled Low at the same time, as would occur during a normal write operation from the microprocessor to the DSC circuit. No data will be transferred by this operation. The HSW hookswitch pin changes state, and the hookswitch interrupt is enabled.
Active Voice and Data Mode
In Active Voice and Data mode all functional blocks of the DSC/IDC circuit are available. Device registers may be accessed through the MPI, the LIU and DLC are available, the OSC is running, the Peripheral Port is available, MUX connections may be made, the Secondary Tone Ringer may be activated, and the MAP is operational (DSC circuit only).
Active Data Only Mode
Active Data Only mode is similar to Active Voice and Data mode, except that the MAP (DSC circuit only) is disabled to reduce system power consumption. This increases the amount of power available for the Secondary Tone Ringer or microprocessor system during the phases of call setup and teardown, or during a data-only telephone call.
Idle Mode
Idle mode is the RESET default mode of DSC/IDCcircuit operation, and represents an operational state in which power consumption is reduced, yet the microprocessor system is operational to program DSC/IDC circuit registers or perform other required background tasks. Idle mode may also be entered by appropriate programming of the INIT register. In Idle mode, the MCLK output is available to drive the microprocessor system, the MPI is available for programming of DSC/IDC registers, and the LIU is available to initiate or respond to S/T interface activity. The HSW hookswitch interrupt is also available in Idle mode.
*
8
AM79C30A/32A Data Sheet
*
The LIU receiver is enabled, detects an incoming signal on the S/T Interface, and achieves activation as indicated by a transition to state F7. Both the INT pin and the F7 transition interrupt must be enabled for Power-Down mode to be exited. If the LIU is enabled, it may restart the oscillator so that it can identify the activity on the interface. If the activity is determined to be noise, the LIU will stop the oscillator and continue to monitor the line without an interrupt or returning to Idle mode. The IOM-2 Interface is enabled as a clock master and the SBIN input pin goes Low. This indicates that a slave device wants to activate the IOM-2 Interface and communicate with the DSC circuit. Both the INT pin and the IOM-2 timing request interrupts must be enabled for Power-Down mode to be exited. The IOM-2 Interface is enabled as a clock slave and the SCLK input pin goes High. This indicates that the master device is activating the IOM-2 Interface and the DSC circuit must wake up in order to monitor the data. Both the INT pin and the IOM-2 timing request interrupts must be enabled for Power-Down mode to be exited.
There are two events that will trigger the clock speed-up function: 1. The DLC receive FIFO threshold has been reached; or, 2. a second packet begins to be received while data from a prior packet is still in the receive FIFO. The second packet case requires provision of an interrupt; see the DLC register section for further information. The clock speed-up function allows the user to program a very slow MCLK frequency using INIT2 when D-channel activity is minimal. If a burst of activity is seen on the D channel and it exceeds the programmed threshold of the receive FIFO or threatens to overrun the receive FIFO status buffers, MCLK will instantly toggle back to the higher frequency programmed in the INIT register. This eliminates the latency incurred if an interrupt has to be serviced to change the clock speed, and allows the overall system power to be reduced during typical voice connections. Note that automatic clock speed-up will not function unless at least one of the associated interrupts are enabled so the processor can be informed that the clock speed has been altered.
*
*
If the DSC/IDC circuit is awakened by any condition other than RESET, the MCLK output will be restored to its previously programmed frequency, and will not generate any shortened or spurious output cycles. If the DSC/IDC circuit is revived by RESET, MCLK will default to its normal 6.144-MHz rate. The DSC/IDC circuit provides a minimum of two MCLK cycles prior to activating the interrupt pin when exiting Power-Down mode.
Global Register Functions
INIT Register (INIT) default = 00H Address = Indirect 21 Hex, Read/Write
Table 1.
Bit 7 6 5 43 2 1
INIT Register
MCLK Frequency Control
The MCLK frequency selection bits in the INIT register are unchanged from Revision D. However, additional MCLK frequencies are available by programming bits in the INIT2 register. No shortened or spurious clock pulses that might disrupt the external microprocessor will result when the MCLK frequency is changed. In order to reduce the probability of errant software disrupting system operation, the INIT2 register requires two consecutive writes before the value will be entered into the register. Note that there will be no MCLK countdown as is the case for entering Power-Down mode if INIT2 is programmed to cause MCLK to STOP, and there will be no shortened or spurious MCLK pulses.
0 Function 0 Idle mode 1 Active Voice and Data mode 0 Active Data Only mode 1 Power-Down mode
XX XX XX XX XX XX XX XX XX XX XX XX XX XX X0 X1 0X 1X
XXXX0 XXXX0 XXXX1 XXXX1
X X X 0 X X INT output enabled X X X 1 X X INT output disabled 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 X X X MCLK frequency = 6.144 MHz 1 X X X MCLK frequency = 12.288 MHz 0 X X X MCLK frequency = 3,072 MHz 1 X X X MCLK frequency = 6.144 MHz 0 X X X MCLK frequency = 4.096 MHz 1 X X X MCLK frequency = 6.144 MHz 0 X X X MCLK frequency = 6.144 MHz 1 X X X MCLK frequency = 6.144 MHz
MCLK Clock Speed-up Function
A programmable automatic MCLK speed-up option is provided that will force a hardware reset of INIT2 bits 3-0, which will cause the MCLK frequency to be restored to the value programmed in the INIT register.
X X X X X X DLC receiver abort disabled X X X X X X DLC receiver abort enabled X X X X X X DLC transmitter abort disabled X X X X X X DLC transmitter abort enabled
AM79C30A/32A Data Sheet
9
INIT2 Register (INIT2) default = 00H Address = Indirect 20 Hex, Read/Write A special write procedure must be followed in order to modify the contents of the INIT2 Register, since the INIT2 Register includes control bits which could result in the stopping of the microprocessor clock. This procedure greatly reduces the probability of errant software disabling the system, and is described as follows: 1. Write the INIT2 address to the Command Register. 2. Write to the Data Register (INIT2 is not yet updated). 3. Write the INIT2 address to the Command Register. 4. Write to the Data Register (INIT2 is updated). The writes must take place without any intervening indirect accesses to the DSC/IDC circuit.
RESET Operation
The AM79C30A/32A can be reset by driving the RESET pin High. When power is first supplied to the DSC/IDC circuit, a reset must be performed. This initializes the DSC/IDC circuit to its default condition as defined in Table 3.
Table 3.
Pin Name D7-D0 MCLK INT SBOUT SFS SCLK
Reset Pin Conditions
State Following RESET High Impedance 6.144 MHz Logical 1 High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance
Table 2.
Bit 7 6 5 4 3 2 1
INIT2 Register
0 Function
LS1, LS2 EAR1 EAR2 AREF LOUT1 LOUT2
00 00
X X X X X X Reserved, must be written to 0; READs are undefined 0 X X X X X Power-Down disabled; writing 11 to the INIT Register will put the DSC/IDC circuit into Idle mode 1 X X X X X Power-Down enabled; writing 11 to the INIT Register will put the DSC/IDC circuit into Power-Down mode X 0 X X X X Multiframe Interrupt filter disabled X 1 X X X X Multiframe Interrupt filter enabled (see LIU section for detailed description) X X X 0 X X Clock speed-up option disabled X X X 1 X X Clock speed-up option enabled; if set, this register bit will be cleared when the DLC FIFO receive threshold or second packet received interrupt is triggered XXX0 XXX0 XXX0 XXX0 XXX1 XXX1 XXX1 XXX1 0 0 1 1 0 0 1 1 0 MCLK frequency determined by INIT Register 1 MCLK frequency is 1.536 MHz 0 MCLK frequency is 768 kHz 1 MCLK frequency is 384 kHz 0 MCLK stopped in High state 1 Reserved 0 Reserved 1 Reserved
Receive and Transmit Abort Commands
The microprocessor has the option via INIT Register bits 6 and 7 to abort the receive and transmit D-channel packets. When the microprocessor sets one of these bits, the AM79C30A/32A aborts the respective operation. The frame abort sequence is defined in greater detail later. (See the Data Link Controller section on page 36.)
00
00 00
Interrupt Handling
The AM79C30A/32A generates either no interrupt or only one interrupt every 125 s. Once asserted, INT remains active until the microprocessor responds by interrogating the AM79C30A/32A's Interrupt Register (IR) (see Table 4). Reading the IR in response to an activated INT pin deactivates the INT pin and clears the IR. If an event causing an interrupt occurs while the IR is being read by the microprocessor, the effect of the event is held until the microprocessor has completed its read cycle. A reset clears all conditions causing interrupts. Bits 0, 1, and 4 of the IR, if set, advise the microprocessor that the respective buffer is ready for reading or writing. If bit 0 is set due to an empty buffer, the D-channel Transmit buffer must be serviced within 375 s. If bit 1 is set and the D-channel Receive buffer is full, the buffer must be serviced within 425 s. This is to prevent erroneous data transfers causing transmitter underrun and receiver overrun errors. If bit 4 is set then the Bb or
00 00
00 00 00 00 00 00 00 00
10
AM79C30A/32A Data Sheet
Bc buffers must be accessed within 122.4 s. This is to prevent erroneous data transfers. Only one interrupt is used to signal accessibility for both B channels of the S Interface. Since the data transfer must occur synchronously to the S Interface, any data access to either Bb or Bc or both must be made within the122.4 s limit. Note that even though only a single interrupt is issued, either or both S-Interface B channels must be serviced. IR bits 2, 3, 5, 6, and 7, if set, indicate that a bit has been set in the associated status or error register. All of the interrupts generated by the AM79C30A/32A can be
individually disabled. In the case of IR bit 7, the interrupt can also be masked by setting PPIER bit 7 to 0. DMR1, DMR2, DMR3, LMR2, MCR4, and MF control the mask conditions that affect the INT pin. The INT pin is activated only by interrupts that are not disabled. The Interrupt Register reflects the status of enabled interrupts. The INT pin can be disabled by setting INIT Register bit 2 to a logical 1. The AM79C30A/32A has facilities that allow the microprocessor to read the status registers (status update is inhibited during status read) or the IR at any time during functional operation.
AM79C30A/32A Data Sheet
11
Table 4.
Bit 0 1 2
Format of the Interrupt Register (IR), Read Only
Interrupt Mask DMR1 bit 0 DMR1 bit 1
Interrupt Generated/Action Required D-channel transmit threshold interrupt/load D-channel Transmit buffer D-channel receive threshold interrupt/read D-channel Receive buffer D-channel status interrupt/read DSR1 Source DSR1 bit 0 DSR1 bit 1 DSR1 bit 6 Cause Valid Address (VA) or End of Address (EOA) When a closing flag is received or a receive error occurs When a closing flag is transmitted DMR3 bit 1 Cause Current received packet has been aborted Non-integer number of bytes received Collision abort detected FCS error Overflow error Underflow error Overrun error Underrun error Receive packet lost
DMR3 bit 0 DMR1 bit 3 DMR3 bit 1
3
D-channel error interrupt/read DER and DSR2 bit 2 Source DER bit 0 DER bit 1 DER bit 2 DER bit 3 DER bit 4 DER bit 5 DER bit 6 DER bit 7 DSR2 bit 2 DMR2 bit 0 DMR2 bit 1 DMR2 bit 2 DMR2 bit 3 DMR2 bit 4 DMR2 bit 5 DMR2 bit 6 DMR2 bit 7 DMR3 bit 6 MCR4 bit 3
4 5
Bb or Bc byte available or buffer empty interrupt/read or write Bb or Bc buffers LIU status interrupt/read LSR Source LSR bit 3 LSR bit 4 LSR bit 5 LSR bit 7 Cause Change of state to F3 Change of state from/to F7 Change of state from/to F8 HSW change of state Cause Last byte of received packet Receive byte available Last byte transmitted Transmit buffer available Start of second packet Cause S-data available Q-bit buffer empty Multiframe change of state (in/out of sync) Monitor receive, data available Monitor transmit, buffer available Monitor EOM received Monitor abort received C/I channel 0, data change C/I channel 1, data change IOM-2 timing request
LMR2 bit 3 LMR2 bit 6 LMR2 bit 4 LMR2 bit 5
6
D-channel status interrupt/read DSR2 Source DSR2 bit 0 DSR2 bit 1 DSR2 bit 3 DSR2 bit 4 DSR2 bit 7 DMR3 bit 2 DMR3 bit 3 DMR3 bit 4 DMR3 bit 5 EFCR bit 1
7
Multiframe or PP interrupt/read MFSB and PPSR Source MFSB bit 5 MFSB bit 6 MFSB bit 7 PPSR bit 0 PPSR bit 1 PPSR bit 2 PPSR bit 3 PPSR bit 4 PPSR bit 5 PPSR bit 6 MF bit 1 MF bit 2 MF bit 3 PPIER bit 0 PPIER bit 1 PPIER bit 2 PPIER bit 3 PPIER bit 4 PPIER bit 5 PPIER bit 6
12
AM79C30A/32A Data Sheet
FUNCTIONAL DESCRIPTION Microprocessor Interface (MPI)
The AM79C30A/32A can be connected to any general purpose 8-bit microprocessor via the MPI. The MCLK from the AM79C30A/32A can be used as the clock for the microprocessor. The MPI is an interrupt-driven interface containing all the circuitry necessary for access to the internal programmable registers, status registers, coefficient RAM, and transmit/receive buffers. MPI External Interface External connections to the MPI are shown in Table 5.
Direct Registers
Access to the Direct Registers of the AM79C30A/32A is controlled by the state of the CS, RD, WR, A2, A1, and A0 input pins, as defined below by Table 6.
Indirect Registers
To read from or write to any of the Indirect Registers, an indirect address command is first written to the Command Register (CR). One or more data bytes may then be transferred to or from the selected register through the Data Register (DR). Registers within certain groups can be accessed quickly by using internal circuitry which automatically increments the indirect value. In Table 7, the bytes transferred numbers are the number of bytes which are read or written to the DR after the CR has been loaded. Whenever the CR is loaded, any previous commands are automatically terminated.
Table 5.
Name D7-D0 A2-A0 RD WR CS RESET INT
MPI External Interface
Function Data Bus Address Line Read Enable Write Enable Chip Select Initialization Interrupt
Direction Bidirectional Inputs Input Input Input Input Output
Table 6.
CS 0 0 0 0 0 0 0 0 0 0 0 0 0 1 RD 1 0 1 0 0 0 1 0 1 0 1 0 0 X WR 0 1 0 1 1 1 0 1 0 1 0 1 1 X A2 0 0 0 0 0 0 1 1 1 1 1 1 1 X A1 0 0 0 0 1 1 0 0 0 0 1 1 1 X A0 0 0 1 1 0 1 0 0 1 1 0 0 1 X
Direct Register Access Guide
Mode W R W R R R W R W R W R R --
Register(s) Accessed Command Register (CR) Interrupt Register (IR) Data Register (DR) Data Register (DR) D-channel Status Register 1 (DSR1) D-channel Error Register (DER) (2-byte FIFO) D-channel Transmit buffer (DCTB) (8- or 16-byte FIFO) D-channel Receive buffer (DCRB) (8- or 32-byte FIFO) Bb-channel Transmit buffer (BBTB) Bb-channel Receive buffer (BBRB) Bc-channel Transmit buffer (BCTB) Bc-channel Receive buffer (BCRB) D-channel Status Register 2 (DSR2) No access (X = logical 0 or 1)
Note: The RD and WR signals must never both be Low under normal operating conditions.
AM79C30A/32A Data Sheet
13
Table 7.
Operation Block Register INIT INIT LIU LIU LIU LIU LIU LIU LIU LIU MUX MUX MUX MUX MUX MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP DLC DLC DLC DLC DLC Initialization Register Initialization Register 2 LIU Status Register LIU Priority Register LIU Mode Register 1 LIU Mode Register 2 -- Multiframe Register Multiframe S-bit/Status Register Multiframe Q-bit buffer MUX Control Register 1 MUX Control Register 2 MUX Control Register 3 MUX Control Register 4 -- X filter Coefficient Register R filter Coefficient Register GX Gain Coefficient Register GR Gain Coefficient Register GER Gain Coefficient Register Sidetone Gain Coefficient Register Frequency Tone Generator Register 1, 2 Amplitude Tone Generator Register 1, 2 MAP Mode Register 1 MAP Mode Register 2 -- MAP Mode Register 3 Secondary Tone Ringer Amplitude Secondary Tone Ringer Frequency Transmit Peak Register Receive Peak Register -- First Received Byte Address Registers 1, 2, 3 Second Received Byte Address Registers 1, 2, 3 Transmit Address Register D-channel Receive Byte Limit Register D-channel Transmit Byte Count Register
Indirect Register Access Guide
Register Number 1 2 1 2 3 4 5 6 7 8 1 2 3 4 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 Indirect Name INIT INIT2 LSR LPR LMR1 LMR2 Perform 2-4 MF MFSB MFQB MCR1 MCR2 MCR3 MCR4 Perform 1-4 X Coeff. R Coeff. GX Coeff. GR Coeff. GER Coeff. STG Coeff. FTGR1, FTGR2 ATGR1,ATGR2 MMR1 MMR2 Perform 1-10 MMR3 STRA STRF PEAKX PEAKR Perform 15-16 FRAR 1, 2, 3 SRAR1, 2, 3 TAR DRLR DTCR Mode Address R/W R/W R R/W R/W R/W - R/W R W R/W R/W R/W R/W -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W R/W R/W R R R R/W R/W R/W R/W R/W 21H 20H A1H A2H A3H A4H A5H A6H A7H A8H 41H 42H 43H 44H 45H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 70H 71H 72H 81H 82H 83H 84H 85H One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred MCR1, 2, 3, 4 h0 LSB, h0 MSB...h7 MSB h0 LSB, h0 MSB...h7 MSB LSB, MSB LSB, MSB LSB, MSB LSB, MSB FTGR1, 2 ATGR1, 2 One byte transferred One byte transferred 46 bytes loaded 1-10 One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred FRAR1, 2 SRAR1, 2 LSB, MSB LSB, MSB LSB, MSB Byte Sequence One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred
14
AM79C30A/32A Data Sheet
Table 7.
Operation Block Register DLC DLC DLC DLC DLC DLC DLC DLC DLC DLC DLC DLC DLC PP PP PP PP PP PP PP PP PP PP PP D-channel Mode Register 1 D-channel Mode Register 2 --
Indirect Register Access Guide (Continued)
Register Number 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 Indirect Name DMR1 DMR2 Perform 1-7 DRCR RNGR1 (LSB) RNGR2 (MSB) FRAR4 SRAR4 DMR3 DMR4 Perform 12-15 ASR EFCR PPCR1 PPSR PPIER MTDR MRDR CITDR0 CIRDR0 CITDR1 CIRDR1 PPCR2 PPCR3 Mode Address R/W R/W -- R R/W R/W R/W R/W R/W R/W -- R R/W R/W R R/W W R W R W R R/W R/W 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H C0H C1H C2H C3H C3H C4H C4H C5H C5H C8H C9H Byte Sequence One byte transferred One byte transferred 4 bytes loaded 1-7 LSB, MSB One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred FRAR4, SRAR4, DMR3, DMR4 One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred
D-channel Receive Byte Count Register Random Number Generator Register Random Number Generator Register First Received Byte Address Register 4 Second Received Byte Address Register 4 D-channel Mode Register 3 D-channel Mode Register 4 -- Address Status Register Extended FIFO Control Register Peripheral Port Control Register 1 Peripheral Port Status Register Peripheral Port Interrupt Enable Register Monitor Transmit Data Register Monitor Receive Data Register C/I Transmit Data Register 0 C/I Receive Data Register 0 C/I Transmit Data Register 1 C/I Receive Data Register 1 Peripheral Port Control Register 2 Peripheral Port Control Register 3
Line Interface Unit (LIU)
The LIU connects to the four-wire S Interface through a pair of isolation transformers, one for the transmit and one for the receive direction, as shown in Figure 1. The receiver section of the LIU consists of a differential receiver, circuitry for bit timing recovery, circuitry for detecting High and Low marks, and a frame recovery circuit for frame synchronization. The receiver converts the received pseudo-ternary coded signals to binary before delivering them to the other blocks of the AM79C30A/32A. It also performs collision detection (Eand D-bit comparison) per the CCITT recommenda-
tions so several TEs can be connected to the same S Interface. The transmitter consists of a binary to pseudo-ternary encoder and a differential line driver which meets the CCITT recommendations for the S Interface. The AM79C30A/32A can establish multiframe synchronization, receive S bits, and transmit Q bits synchronized to the received frame. External Interface The LIU can be connected to both point-to-point and point-to-multipoint configurations at the CCITT S reference point. The point-to-point configuration consists of one TE connected to the NT or PABX linecard. The
AM79C30A/32A Data Sheet
15
point-to-multipoint configuration can have multiple TEs connected to one NT. Line Code Pseudo-ternary coding is used for both transmitting and receiving over the S Interface. In this type of coding, a binary 1 is represented by a space (zero voltage), and a binary 0 is represented by a High mark or a Low mark. Two consecutive binary 0s are represented by alternate marks to reduce DC offset on the line. A mark followed, either immediately or separated by spaces, by a mark of the same polarity, is defined as a code violation. Code violations are used to identify the boundaries of the frame.
Note: The DSC defines "Any Signal" as any frame with at least three marks above receive threshold.
(bit 7 of the Multiframe Register) and multiframe change of state bit (bit 7 of the Multiframe S bit/Status buffer) are set. Note that S-bit data is received, compiled, and transferred to the user after attaining synchronization at the start of the next multiframe. S-Bit Reception The default operation of the DSC/IDC circuit is that the LIU will receive and pass multiframe data to the user in 5-bit increments four times per multiframe, regardless of the value of the data. After multiframe synchronization has been requested and established the microprocessor can read the Multiframe S bit/Status buffer (MFSB) once the S-bit available bit (MFSB bit 5) is set. The S-data available bit is set to a logical 1 when the AM79C30A/32A has received five S bits (one S bit per S-interface frame) synchronized to the setting of the FA -bit to a logical 1 and transferred them into the MFSB. Once the S-bit available bit is set, the MFSB must be accessed within 1.25 ms or succeeding S data will be lost. Subsequent to the original definition of the DSC/IDC circuit, the CCITT has defined a structure for the 20 multiframe bits, which specifies five 4-bit channels. Furthermore, the idle code for these channels has been defined as 0000. An enhanced mode of multiframe reception has been included, which may be enabled by setting INIT2 bit 4 to a 1. This enhanced mode reduces processor overhead by generating an interrupt only upon the reception of a non-zero S-channel word. INIT2 bit 4 will be automatically cleared by hardware when the five received data bits in the MFSB are not all 0s, as long as MF bit 1 (interrupt enable) is set. This allows subsequent valid all-zero words to be received. Furthermore, when the first five S bits of the multiframe are loaded into the MFSB, bit 4 of the MF register will be set, which allows identification of the position of received words within the multiframe.
Frame Structures In both transmit and receive directions, the bits are grouped into frames of 48 bits each. The frame structure is identical for both point-to-point and point-to-multipoint configurations. Each frame transmitted at 4 kHz consists of several groups of bits. Multiframing If multiframing is enabled, the AM79C30A/32A recognizes and establishes multiframe synchronization based on the monitoring of the FA (Q-bit control) and M (M-bit control) bits. The AM79C30A/32A also receives and compiles S bits, and transmits Q bits synchronized to the received frame. Establishment of Multiframe Synchronization When the enable multiframe synchronization bit (bit 0 of the Multiframe Register) is set and the LIU is in either state F6 or F7, the LIU monitors the FA (Q-bit control) and M (M-bit control) bits. When three consecutive multiframes with the M bits and FA bits set as defined in Table 8 are received, the multiframe synchronized bit
S Line Drivers Binary to Pseudo-ternary Coder
To MUX and DLC Decoder
Frame Recovery
Slicer Timing Recovery Balanced Receiver
09893H-2
Figure 1.
LIU Block Diagram
16
AM79C30A/32A Data Sheet
Table 8.
Frame Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 etc. NT-to-TE Q Control Bit FA 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0
Multiframing Structures
NT-to-TE M Bit (M) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 NT-to-TE S Bit (S) SC11 SC21 SC31 SC41 SC51 SC12 SC22 SC32 SC42 SC52 SC13 SC23 SC33 SC43 SC53 SC14 SC24 SC34 SC44 SC54 SC11 SC21 TE-to-NT FA Bit (Q Bit) Q1 0 0 0 0 Q2 0 0 0 0 Q3 0 0 0 0 Q4 0 0 0 0 Q1 0
Transmission of Q bits The microprocessor can load the Multiframe Q-bit buffer (MFQB) once the Q-bit buffer empty bit (bit 6 of the Multiframe S bit/Status buffer) is set. The Q-bit buffer empty bit is set to a logical 1 at reset or when data that has been written to the Multiframe Q-bit buffer is transferred to the LIU. The Q-bit buffer empty bit is cleared to a logical 0 when the Multiframe S-bit/Status buffer is read. After multiframing has been requested and established, the AM79C30A/32A transfers the data written into the Q-bit Register to the LIU, synchronized to the multiframe, irrespective of the receipt of valid Q-control bits. If the microprocessor does not reload the Q-bit Register for retransmissions, the Q-bit pattern is repeated in the next multiframe. If multiframing is enabled but multiframe synchronization is not established, the LIU transmits the value loaded in MFQB bit 4 in all Q bits. The default value of MFQB bit 4 is a logical 0 which satisfies the CCITT recommendations. When synchronization is achieved, the contents of MFQB bits 3 to 0 are transmitted according to Table 8.
Loss of Multiframe Synchronization The AM79C30A/32A continuously monitors the FA (Q-bit control) and the M bits to ensure multiframe synchronization. Once multiframe synchronization is established, multiframe synchronization is lost if three consecutive invalid multiframes are received, or the LIU is no longer in state F6 or F7, or multiframing is disabled. When loss of multiframe synchronization occurs, bit 7 of the Multiframe Register is set to a logical 0, and bit 7 of the Multiframe S bit/Status buffer is set to a logical 1. The AM79C30A/32A also terminates the reception of S bits and transmission of Q bits until multiframing synchronization is re-established.
HSW
The hookswitch circuitry on the DSC circuit provides the attached microprocessor with a way of converting an external mechanical hookswitch into a software status condition capable of generating an interrupt. Debounce and glitch rejection are provided internal to the DSC circuit. The logic rejects glitches less than 162 ns and provides debounce of 16 ms. HSW status reporting is disabled after RESET. It is enabled by any of the following: taking the device out of Idle mode, a write to a MUX Control Register (MCR3-MCR1), or unmasking the HSW interrupt.
AM79C30A/32A Data Sheet
17
LIU Registers The LIU contains the registers shown in Table 9.
Table 9.
Registers LIU Status Register LIU Priority Register LIU Mode Registers Multiframe Register Multiframe S-bit/Status Register Multiframe Q-bit buffer
LIU Registers
No./Registers Mnemonic 1 1 2 1 1 1 LSR LPR LMR1, LMR2 MF MFSB MFQB
as 1, F4 as 2, and so on, where bit 0 is the LSB. The LIU interrupts the microprocessor via bit 4 of the LSR when activation has been achieved (that is, when the LIU moves to state F7 upon receipt of INFO 4). During reset the LSR is 0. Even thou gh th e L IU Status R eg iste r ( LSR ) is read-only, no default value upon power-up is given due to the uncertain state of bit 6 (Hookswitch State). Following RESET, the LIU State is F2 and the HSW bit reflects the HSW pin, producing a power-up value of either 00H or 40H. LIU D-Channel Priority Register (LPR), Read/Write The LPR contains the priority level for D-channel access. Its default value after reset is 0. The D-channel access procedure of the AM79C30A/ 32A uses the priority level programmed in the LPR. The priority mechanism defined by the CCITT I-series recommendations is fully implemented if the LPR is programmed via the microprocessor to conform to the priority class of the Layer-2 frame to be transmitted.The LPR has 16 possible programmable priority levels. The priority levels are numbered 0-15. Priority Level 0 corresponds to counting eight 1s in the echo channel, priority Level 1 corresponds to counting ten 1s in the echo channel, priority Level 2 corresponds to counting twelve 1s, etc. The DSC circuit automatically handles transitions between the programmed priority level n and the associated odd value n + 1. The priority is incremented following a successfully transmitted packet, and decremented when the higher count has been satisfied. The LPR format is shown in Table 11.
LIU Status Register (LSR), Read Only Address = Indirect A1H The LSR format is shown in Table 10.
Table 10.
Bit 0-2
LIU Status Register
Generates Interrupt No
Logical 1 Binary values 000 through 110 represent the LIU activation circuitry's current state (F2 through F8, respectively) bit 2 is MSB Change of state to F3 Change of state from/to F7 Change of state from/to F8 HSW state HSW change of state
3 4 5 6 7
If LMR2 bit 3 = 1 If LMR2 bit 6 = 1 If LMR2 bit 4 = 1 No If LMR2 bit 5 = 1
Table 11.
Bits 3, 2, 1, 0 7, 6, 5, 4
LIU Priority Register
Description
When the microprocessor reads the LSR, bits 3, 4, 5, and 7 are cleared. The other bits retain the current status of the LIU. bits 0 to 2 are defined such that state F2 (see CCITT I.430 state matrix tables) is coded as 0, F3
D-channel access priority level bit 0 is LSB Reserved, reads logical 0
18
AM79C30A/32A Data Sheet
LIU Mode Register (LMR1), Read/Write Address = Indirect A3H LMR1 is defined in Table 12.
Table 12.
Bit 0 1 2 3 4 5 6 7 Logical 1 Enable B1 transmit Enable B2 transmit Disable F transmit Disable FA transmit Activation request Go from F8 to F3 Enable receiver/transmitter Reserved; must be set to logical 0
LIU Mode Register 1
Logical 0 (default value) Disable B1 transmit Disable B2 transmit Enable F transmit Enable FA transmit No activation request No transition Disable receiver/transmitter Reserved; must be set to logical 0
Notes: The F and FA bits in LMR1 (bits 2 and 3) should be enabled during the activation procedure so the AM79C30A/32A can respond with INFO 3. LMR1 bit 4 is used to transfer the signals PH-AR and Expiry of Timer from the microprocessor to the LIU (see CCITT I.430 state diagram--activation request). PH-AR is defined as bit 4 being a logical 1 and Expiry of Timer is defined as the transition of bit 4 from a logical 1 to a logical 0. This bit must not be set until the LIU, as reflected in the LSR, is in state F3, F6, or F7 and the receiver has been enabled for a minimum of 250 s. LMR1 bit 6 is primarily used to disable the receiver when the terminal does not require access to the S Interface signals. This bit is cleared by reset and must be written to logical 1 in order to receive activation from the S Interface, or to request activation.
LIU Mode Register 2 (LMR2), Read/Write Address = Indirect A4H LMR2 is used to select the operations found in Table 13.
Table 13.
Bit 0 1 2 3 4 5 6 7 Logical 1
LIU Mode Register 2
Logical 0 (Default Value) D-channel loopback at AM79C30A/32A disable D-channel loopback at LIU disable D-channel back-off enable F3 change of state interrupt disable F8 change of state interrupt disable HSW interrupt disable F7 change of state interrupt disable Reserved; must be set to logical 0
D-channel loopback at AM79C30A/32A enable D-channel loopback at LIU enable D-channel back-off disable F3 change of state interrupt enable F8 change of state interrupt enable HSW interrupt enable F7 change of state interrupt enable Reserved; must be set to logical 0
AM79C30A/32A Data Sheet
19
The three D-channel loopback controls defined in LMR2 bits 0, 1, and 2 are explained below: Bit 0, D-channel loopback at AM79C30A/32A enable:
Bit 1, D-channel loopback at LIU enable: AM79C30A D S D NT/PABX
AM79C30A
D D
S
D D
NT/PABX MPI This local loopback is provided for local testing. Data on the incoming D channel is ignored. The data from the microprocessor is processed by the DLC and then looped back to the microprocessor. Bit 2, D-channel back-off disable:
E
This remote loopback is provided for maintenance purposes from the NT's perspective. The NT transmits D-channel bits to the AM79C30A/32A where they are internally looped (with the Data Link Controller) and transmitted back to the NT. The incoming D-channel data can be accessed by the microprocessor; however, the microprocessor cannot send data on the outgoing D channel. Any difference between the transmitted D-channel bits a n d t h e r e c e i ve d E - c h a n n e l b i t s t o / f r o m t h e AM79C30A/32A (normally detected as an error which halts the transmission) is ignored, thereby allowing the transmission to continue.
AM79C30A
D E
S
D E
NT/PABX
This loopback is provided for maintenance purposes from the TE's perspective. The AM79C30A/32A transmits D-channel bits to the NT where they are looped and transmitted back to the AM79C30A/32A in the E channel. The operation is normal except differences between the D and E channels do not halt the transmission.
Multiframe Register (MF), Read/Write Address = Indirect A6H Table 14.
Bit 0 1 2 3 4 5, 6 7 Logical 1 Enable Multiframe sync Enable S-data available interrupt Enable Q-bit buffer empty interrupt Enable Multiframe change of state interrupt First subframe Not used, reads logical 0 Multiframe synchronized (read only)
Multiframe Register
Logical 0 (Default Value) Disable Multiframe sync Disable interrupt Disable interrupt Disable interrupt Not first subframe Not used, reads logical 0 Multiframe not synchronized (read only)
20
AM79C30A/32A Data Sheet
Multiframe S-bit/Status Buffer (MFSB), Read Only Address = Indirect A7H
The logical channels available at the MUX are shown in Figure 2, They are: 1. From/to the LIU channels B1 and B2
Table 15.
Bit 0 1 2 3 4 5 6 7 S1 S2 S3 S4 S5
Multiframe S-Bit/Status Buffer
Generates Interrupt No No No No No If MF bit 1 = 1 If MF bit 2 = 1
2. From/to the MAP channel Ba 3. From/to the MPI channels Bb and Bc 4. From/to the PP channels Bd, Be, and Bf For any specific application, the MUX can be programmed by the microprocessor to route any three B- ch an n el p or ts to a ny o the r thr ee B- ch a nn e l ports.Programmable bidirectional bit reversal is provided for both of the MPI data channels Bb and Bc. MUX Control Registers 1, 2, and 3 (MCR1, MCR2, and MCR3), Read/Write Addresses = Indirect 41H, 42H, 43H The MUX can support three bidirectional paths. The contents of the MUX Control Registers MCR1, MCR2, and MCR3 direct the flow of data between the eight MUX logical B channels (see Figure 2). These three MCRs are programmed to connect any two B-channel ports together by writing the appropriate channel code into an MCR. These MCRs have the same format, where bits 7-4 indicate port 1 and bits 3-0 indicate port 2. In each of these three MCR registers, the channel codes found in Table 18 are used for both ports 1 and 2.
Description
S-data available Q-bit buffer empty
Multiframe change of state If MF bit 3 = 1
The MFSB reset default value is 40H. Multiframe Q-bit Buffer (MFQB), Write Only Address = Indirect A8H
Table 16.
Bit 0 1 2 3 4 5, 6, 7
Multiframe Q-Bit Buffer
Description Q1 (default = 1) Q2 (default = 1) Q3 (default = 1) Q4 (default = 1) Q-bit value when multiframing enabled but synchronization not achieved (default = 0) Not used
Table 18.
Code 0000 0001 0010
MCR Register Channel Codes
Channel No connection (default value) B1 (LIU) B2 (LIU) Ba (MAP) Bb (MPI) Bc (MPI) Bd (PP channel 1) Be (PP channel 2) Bf (PP channel 3)
Multiplexer (MUX)
The MUX contains the registers found in Table 17.
0011 0100 0101
Table 17.
Register MUX Control Registers
MUX Registers
Mnemonic MCR1, MCR2, MCR3, MCR4
0110 0111 1000
No./Registers 4
The Multiplexer is used to selectively route 64-Kbit/s full-duplex B channels between the LIU (Line Interface Unit), MAP (Main Audio Processor), MPI (Microprocessor Interface), and the PP (Peripheral Port).
For example, to connect B1(LIU) with Bb (MPI) and B2 (LIU) with Ba (MAP), the contents of the MCRs would be: Port 1 Port 2
Register 7 6 5 4 3 2 1 0 Channel Connection MCR1 MCR2 MCR3 0 0 0 1 0 1 0 0 B1 (LIU) 0 0 1 0 0 0 1 1 B2 (LIU) 0 0 0 0 0 0 0 0 No connect Bb (MPI) Ba (MAP) No connect
AM79C30A/32A Data Sheet
21
Peripheral Port Bd Be Bf
Bb MPI Bc B-channel MUX
B1 LIU B2
Ba MAP
09893H-3
Figure 2.
MUX Logical Channels MCR will overwrite the data from the connecting port in the lower priority MCR, for example:
Port 1 Port 2
Therefore, in this example, MCR1 provides a data link from the S Interface and MCR2 sets up a voice connection across the S Interface. To loopback a channel, the same channel code is used for port 1 and port 2. For example, to loopback B1, B2, and Ba, the MCRs would be:
Port 1 Port 2
Register 7 6 5 4 3 2 1 0 Channel Connection MCR1 MCR2 MCR3 0 0 0 0 0 0 0 0 No connect 0 0 0 1 0 1 0 0 B1 (LIU) 0 1 0 0 0 0 1 1 Bb (MPI) Bb (MPI) Ba (MAP)
Register 7 6 5 4 3 2 1 0 Channel Connection MCR1 MCR2 MCR3 0 0 0 1 0 0 0 1 B1 (LIU) Loopback 0 0 1 0 0 0 1 0 B2 (LIU) Loopback 0 0 1 1 0 0 1 1 Ba (MAP) Loopback
The final data transfers are: B1 (LIU) receives Bb (MPI), Ba (MAP) receives Bb (MPI), Bb (MPI) receives Ba (MAP). Therefore, the data transfer from B1 (LIU) to Bb (MPI) is lost in the arrangement proposed in MCR2.
MCR3 has higher priority than MCR2. MCR2 has higher priority than MCR1. If multiple connections are made to the same port, the data from the connecting ports in the highest priority
22
AM79C30A/32A Data Sheet
MUX Control Register 4 (MCR4), Read/Write Address = Indirect 44H The MUX Control Register 4 (MCR4) can prevent interrupt generation by masking the output of IR bit 4. MCR4 has the format shown in Table 19.
Table 19.
Bit 0-2 3 4 5 6 7 Logical 1 Reserved, must be set to logical 0
MUX Control Register 4
Logical 0 (Default Value) Reserved, must be set to logical 0
Enable Bb- or Bc-channel byte available interrupt (IR Bit 4) Disable interrupt Reverse bit order of Bb (LSB transmitted/received first) Reverse bit order of Bc (LSB transmitted/received first) Reserved, must be set to logical 0 Reserved, must be set to logical 0 No Bb bit reversal (MSB transmitted/received first) No Bc bit reversal (MSB transmitted/received first) Reserved, must be set to logical 0 Reserved, must be set to logical 0
AM79C30A/32A Data Sheet
23
Main Audio Processor (MAP)
(AM79C30A only) Overview The MAP, as illustrated in Figure 3, implements audio-band analog-to-digital (ADC) and digital-to-analog (DAC) conversions together with a wide variety of audio support functions. Analog interfaces are provided for a handset earpiece, a handset mouthpiece, a microphone, and a loudspeaker. A programmable analog preamplifier is included in front of the A/D converter. The codec and filter functions are implemented using digital signal processing (DSP) techniques to provide operational stability and programmable features. There is one programmable digital gain stage in the transmit path and two in the receive path to allow precise signal level control. Sidetone attenuation is programmable, and programmable equalization filters are present in both the receive and transmit paths in order to modify the frequency response of either or both paths. Tone generation capability is included to allow generation of ringing signals, DTMF tones, and call progress signals. MAP operation is described in detail in the following sections.
Audio Inputs The audio input port consists of two inputs (AINA and AINB) which are selectable, one at a time, by register programming. Signals applied to these inputs must be AC-coupled. Earpiece and Loudspeaker Drivers The earpiece and loudspeaker drivers each consist of amplifiers with differential, low-impedance outputs. The MAP receive path signal may be routed to either of these outputs, or to both outputs simultaneously. Alternatively, the MAP receive path may be routed to the EAR outputs while the Secondary Tone Ringer (STR) is routed to the LS outputs. The EAR drivers can drive loads S130 ohms between the EAR1 and EAR2 pins, while the LS drivers can drive loads S40 ohms between the LS1 and LS2 pins. The maximum capacitive-loading between EAR1 and EAR2 or between LS1 and LS2 is 100 pF. The EAR outputs are high-impedance when the MAP is disabled. The LS outputs are high impedance when both the MAP and the Secondary Tone Ringer are disabled.
CAP1 CAP2 AINA AINB AREF Analog Sidetone Gain* EAR1 EAR2 DAC LS1 LS2
Notes: Minimum GX GER GR STG GA ASTG 0 dB** -10 dB** -12 dB** -18 dB** 0 dB -27 dB** Default 0 dB 0 dB 0 dB -18 dB 0 dB 8 Maximum 12 dB 18 dB 0 dB 0 dB 24 dB -6 dB
PEAKX GA* ADC Decimators, BPF Digital Loopback 1 (A) DTMF GEN. Sidetone Gain* X* GX* COMP* Ba channel to MUX
Transmitter Receiver
Digital Loopback 2 Interpolators, LPF R* GER* + GR*
Ba channel from EXP* MUX
STR* (C)
Step 0.5 dB 0.5 dB 0.5 dB 0.5 dB 6.0 dB 1.5 dB
PEAKR Tone* Ringer Tone* Gen. (B)
*Programmable **These registers can also be programmed for infinite attenuation to break the signal path if desired.
09893H-4
Figure 3.
Main Audio Processor Block Diagram
24
AM79C30A/32A Data Sheet
Programmable Analog Preamplifier A programmable analog preamplifier GA is included in front of the A/D converter and is adjustable in 6-dB increments from 0 dB to +24 dB. The existing GX gain stage in the transmit path may be used for finer adjustment of transmit gain. This preamplifier eliminates the need for an external operational amplifier when interfacing electret-type handsets to the DSC circuit. Analog Sidetone Analog sidetone takes the analog input to the transmitter ADC and sums it into the single-ended input of the EAR output buffer. The summing point is after the output selection switch. The analog sidetone path has programmable attenuation between -6 and -27 dB, plus infinity (off). Default is infinity. Programming is via four bits in the Extended FIFO Control Register, EFCR.6-3. The programming values are given in Table 20.
Receiver
The receiver performs a series of operations described as follows: 1. An expander converts the input A- or -law data to digital linear data. The most significant bit is transferred from the MUX first. The default value is -law. 2. The GR filter is a programmable gain filter that allows the user to program a gain of -12 to 0 dB in 0.5-dB steps. The default value of GR is 0 dB. 3. The GER and Sidetone Gain (STG) are programmable constant multipliers which allow the user to program a gain of -10 to +18 dB in 0.5-dB steps (default value 0 dB) and -18 to 0 dB in 0.5-dB steps (default value -18 dB) respectively. The GER provides volume control (for the hearing impaired) and should be programmed to 0 dB for normal operation. The sidetone gain path provides feedback from the transmitter. 4. The R filter is provided to correct for speaker attenuation distortion and is a user-programmable filter similar to the X filter in the transmitter. 5. A series of interpolators increases the sampling frequency. 6. A DAC converts the digital signal to the analog audio output signal. PEAK Hold Registers Logic in the form of two microprocessor accessible peak hold registers will be provided to allow for support of a software based speaker phone solution. These registers, one in the transmit path (PEAKX) and one in the receive path (PEAKR), will provide the compressed maximum (peak) absolute value of the data in the path since the register was last read. With appropriate software, this can be used to implement a hands-free function. Refer to the MAP block diagram for the location of these registers in the processing path. The following assumptions are made: 1. The GX and GR blocks are used as gain/attenuators, without modification to their range or resolution. 2. The data is presented in compressed A-law format, without the alternate bit inversion. The sign bit is not presented. 3. The data extraction point for the transmit path is after the X filter. 4. The data extraction point for the receive path is immediately following the expander. 5. The compressed data from the transmit and receive paths is presented using the same compression algorithm.
Table 20.
0000 = 0001 = -27.0 dB 0010 = -25.5 dB 0011 = -24.0 dB 1000 = -16.5 dB 1001 = -15.0 dB 1010 = -13.5 dB 1011 = -12.0 dB
Analog Sidetone
0100 = -22.5 dB 0101 = -21.0 dB 0110 = -19.5 dB 0111 = -18.0 dB 1100 = -10.5 dB 1101 = -9.0 dB 1110 = -7.5 dB 1111 = -6.0 dB
Signal Processing
Transmitter
The transmitter performs a series of operations as described below. 1. An ADC converts the incoming analog signal at a sampling rate of 512 kHz. 2. The Band Pass filter and a series of decimators reject DC and 50- to 60-Hz line frequencies while reducing the sampling rate to 8 kHz. 3. The X filter is an 8-tap user-programmable filter for tuning the microphone. The default is flat with unity gain. 4. The GX filter is a programmable gain filter that allows the user to program a gain of 0 to +12 dB in 0.5-dB steps. The default value is 0 dB. 5. The -law or A-law digital compression algorithm converts the linear output of the GX filter to - or A-law code. The default algorithm is -law code. The MSB (sign bit) is transferred first to (or from) the MUX.
AM79C30A/32A Data Sheet
25
6. The peak registers are double-buffered and can be read asynchronously to the operation of the DSP register. They are cleared on read. 7. The peak registers default to "don't care" values when the part is reset. An initial read operation is required to clear the register before using it for the first time. The PEAKX register is at indirect address 70H, while the PEAKR register is at indirect address 71H. Both may be accessed via back-to-back read data register operations by loading the command register with 72H. Tone Generators The MAP contains three tone generators which can be enabled via MAP Mode Register 2, bits 2, 3, and 4. Only one of the three tone generator bits in the register can be set at a time. If more than one bit is set, all three bits are considered set to zero and tone generation is disabled. The tone generators are:
The DTMF generator may be used to generate single frequency outputs. To obtain a single frequency out of the DTMF generator, load a zero code into one of the two frequency registers.
Tone Generation
This generator provides call progress tones to the receive path, where it is added to the incoming speech (Figure 3, Block B).
Tone Ringer
This generator provides tone aler t signals output through the receive path to the loudspeaker or earpiece (Figure 3, Block C). To program the DTMF tone generators, two frequency values and two amplitude values must be written to the two 8-b it Frequ ency Ton e Gen era to r Re gisters (FTGR1, FTGR2) and the two 8-bit Amplitude Tone Generator Registers (ATGR1, ATGR2), respectively. The Tone Generator and the Tone Ringer use the frequency programmed in FTGR1. The Tone Generator uses the amplitude programmed in ATGR1 while the Tone Ringer uses the amplitude programmed in ATGR2. Common frequency values are listed in Table 22. The FTGR codes to obtain DTMF dialing output frequencies are listed in Table 21.
DTMF Generator
This generator provides tone injection at a sampling rate of 32 kHz into the transmit and sidetone paths (Figure 3, Block A). The DTMF frequencies generated are guaranteed to 1.2% deviation.
Table 21.
FTGR 2 or 1 HEX REG VALUE FTGR 1 or 2 5AH 63H 6EH 79H FREQ 697 770 852 941 9BH 1209 1 4 7 *
DTMF Codes
ABH 1336 2 5 8 0 BFH 1477 3 6 9 # D3H 1633 A B C D
26
AM79C30A/32A Data Sheet
The output frequency of the DTMF tone generator approximately equals:
64000 DTMF Frequency in Hz = --------------------------------------------------integer ( 8192 i ) + 1
The ATGR registers allow the user to program a gain of -18 dB to 0 dB in 2-dB steps. Example ATGR codes to obtain amplitude gains are listed in Table 23. 0 dB implies a level of +3 dBm0. The gain values are rounded off to the nearest 1 dB.
where i is the decimal equivalent of value programmed into the FTGR register. This allows the DTMF generator to supply common dual tone call progress signals such as Busy or Dial tones.
Table 23.
-18
Amplitude Gain Coefficients
Hex Code 37 32 31 27 22 21 20 12 11 10
Gain (dB)
Table 22.
Tone Ringer and Tone Generator Frequency Coefficients
Hex Code AB 81 67 56 4A 41 39 34 2F 2B 28 25 23 21 1F 1D 1B 1A 19 18 17 16 15
-16 -14 -12 -10 -8 -6 -4 -2 0
Frequency (Hz) 2666 2000 1600 1333 1142 1000 889 800 727 667 615 571 533 500 471 444 421 400 381 364 348 333 320
Note: See the amendment to Table 23 following page 100.
Secondary Tone Ringer
A Secondary Tone Ringer is included, which is able to ring the phone using the LS outputs while a voice conversation is in progress on the EAR outputs. The STR is louder than the Tone Generator, and may be used with or without enabling the MAP in order to provide flexible control of system power consumption. The STR is not available if the INIT register is programmed to Idle or Power-Down mode. The amplitude and frequency of the STR square-wave output waveform is programmable via the STRA and STRF registers, respectively. If both the LS outputs from the MAP receive path and the STR are simultaneously enabled, priority is given to the STR connection. The STR is available for both the DSC and IDC circuits. A legal value must be programmed in the STRF register before the STR is enabled.
Note: These coefficients do not apply to the DTMF generator.
AM79C30A/32A Data Sheet
27
Programmable Gain Coefficients The GER, GR, GX, and Sidetone gain coefficients are each 16 bits in length. Two consecutive register locations correspond to one gain coefficient. The LSB is transferred first to (or from) the microprocessor. Sample coefficients for the GER filter are listed in Table 24. The gain values are rounded off to the nearest 0.1 dB. Table 24.
Hex Code Gain (dB) -10 -9.5 -9.0 -8.5 -8.0 -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 MSB AA 9B 79 09 41 31 9C 9D 74 54 6A AB AB 74 64 6A 2A BE 5C 75 00 55 43 33 52 77 55 41 LSB AA BB AC 9A 99 99 DE EF 9C 9D AE CD DF 29 AB FF BD EF CE CD 99 4C DD DD EF 1B 42 DD Gain (dB) 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.4 14.0 14.5 15.0 15.5 15.9 16.6 16.9 17.5 18.0 MSB 31 44 43 33 40 11 44 41 31 55 10 42 41 11 60 00 42 40 11 22 72 42 21 10 22 11 00 21 00
GER Gain Coefficients
Hex Code LSB DD 1F 1F 1F DD DD 0F 1F 1F 20 DD 11 0F 1F 0B DD 10 0F 0F 10 00 00 10 0F 00 10 0B 00 0F
Note: The coefficient 0008 provides an attenuation of infinity when GER gain is enabled.
28
AM79C30A/32A Data Sheet
Example coefficients for the GR, GX, and STG filters are listed in Tables 25, 26, and 27. The gain values are rounded off to the nearest 0.1 dB.
Table 26.
Gain (dB) -11.5
GR Gain Coefficients
Hex Code MSB 91 91 92 91 92 92 92 92 93 93 94 9F 9C 9B 9A 9A A2 A2 A6 AA B2 BB CB 08 LSB C5 B6 12 A4 22 32 FB AA 27 B3 B3 91 EA F9 AC 4A 22 A2 8D A3 42 52 B2 08
Table 25.
Gain (dB) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0
GX Gain Coefficients
Hex Code MSB 08 4C 3D 2A 25 22 21 1F 12 12 11 0B 10 03 02 02 01 01 01 00 00 00 00 00 00 LSB 08 B2 AC E5 33 22 22 D3 A2 1B 3B C3 F2 BA CA 1D 5A 22 12 EC 32 21 13 11 0E
-11.0 -10.5 -10.0 -9.5 -9.0 -8.5 -8.0 -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
AM79C30A/32A Data Sheet
29
Table 27.
Gain (dB) -18.0 -17.5 -17.0 -16.5 -16.0 -15.5 -15.0 -14.5 -14.0 -13.5 -13.0 -12.5 -12.0 -11.5 -11.0 -10.5 -10.0 -9.5 -9.0 -8.5 -8.0 -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
STG Gain Coefficients
Hex Code MSB 8B 8B 8B 8B 8B 8B 91 91 91 91 91 91 91 91 91 92 91 92 92 92 92 93 93 94 9F 9C 9B 9A 9A A2 A2 A6 AA B2 BB CB 08 LSB 7C 44 35 2A 24 22 23 2E 2A 32 3B 4B F9 C5 B6 12 A4 22 32 FB AA 27 B3 B3 91 EA F9 AC 4A 22 A2 8D A3 42 52 B2 08
Overflow/Underflow Precautions When Using Programmable Gains Care must be taken so that at any point in the signal processing path, the combination of gains and filters and/or tones does not result in a signal that is larger than full scale. Full scale is defined as the digital representation of the maximum analog signal that is allowed into the transmitter or out of the receiver with all filters and gain stages at their default (0 dB) settings (e.g., in A-Law, the transmitter full scale is 1.25 VP and the receiver full scale is 2.5 VP). Likewise, it is desirable that the peak signal be kept as close to full scale as possible at any point in the signal processing path in order to minimize digital truncation effects in the A/D, D/A, and MAP DSP. Consider the following example: STG is programmed for infinite attenuation, GR is programmed to -6 dB while GER is programmed to +12 dB, and the R filter is programmed to exhibit a net gain of -6 dB. Assume the analog full scale out of the receiver is 2.5 VP, and a full scale PCM code is possible from the MUX. After GR, the equivalent analog signal will be 2.5 / 2 = 1.25 VP. However, after GER the signal will be 1.25 x 4, or + 5 VP. Even though the R filter will have a net gain of -6 dB, the signal will be clipped after GER and distorted for PCM codes between full scale and 6 dB below full scale due to the intermediate result at the output of GER. Be very careful when programming the tone ringers/generators. For example, if one of the DTMF tones is programmed to 0 dB, a tone is generated that is equivalent to a full scale signal in the transmit path. This means no headroom is left for the other DTMF tone. Therefore, the DTMF generator should never be programmed to exceed full scale if signal quality is to be maintained. In the receive path, similar caution should be exercised in order to prevent the combination of Tone Generator, Sidetone, GR, and GER from clipping the signal. Extended Programming Ranges Some applications of the DSC will require greater flexibility in the programming of the MAP's internal gain and attenuation blocks. For example, applications such as software-based hands-free utilizing the PEAKX and PEAKR registers may need attenuation as well as gain within the MAP transmit path. The preceding gain tables do not specifically detail this capability, but due to the DSP implementation of these gain and filter blocks, the DSC is capable of performance beyond these recommended ranges. (GA and ASTG are not implemented in DSP and are limited to their stated range and step size.) Table 28 lists guaranteed ranges, while Table 29 shows the limits by design.
Note: The coefficient 9008 provides an attenuation of infinity when GR, GX, and/or STG are enabled.
30
AM79C30A/32A Data Sheet
Table 28.
GX GER GR STG
Recommended Ranges
Recommended and guaranteed 0 to +12 dB plus infinite in 0.5 dB steps -10 to +18 dB plus infinite in 0.5 dB steps -12 to 0 dB plus infinite in 0.5 dB steps -18 to 0 dB plus infinite in 0.5 dB steps
where each hj Coefficient Register pair has the following format:
Byte LSB MSB 7 S1 S3 654 M1 M3 3 S0 S2 210 M0 M2
and Ai = -1 Si 2 -Mi , (i=0,1,2,3). The X and R filter coefficients are programmed using a 16-byte transfer with the format shown in Table 30.
Table 29.
Limits by design GX GER GR STG
Design Ranges
-84.3 to 14.0 dB plus infinite in 0.1 dB steps over most of the range -24.1 to 24.1 dB plus infinite in 0.1 dB steps over most of the range -84.3 to 14.0 dB plus infinite in 0.1 dB steps over most of the range -84.3 to 14.0 dB plus infinite in 0.1 dB steps over most of the range
Table 30.
Byte 0 1 2 4 5 6 7 8 9 10 11 12 13 14 15
X/R Filter Format
Value h0 LSB h0 MSB h1 LSB h2 LSB h2 MSB h3 LSB h3 MSB h4 LSB h4 MSB h5 LSB h5 MSB h6 LSB h6 MSB h7 LSB h7 MSB
As an example, in a hands-free application using an electret requiring 24 dB of gain in the transmit path for optimum performance. The typical implementation would use 18 dB of GA and 6 dB of GX gain. The user would then have a programmable range of +6 dB to -66 dB utilizing GX. Selection of these gain points is of course, application specific, and will depend on the performance requirements of the system. Listings of the optimized programming values for various levels are included in Appendix A. Values listed in the recommended tables are still correct and will perform as stated. There is no need to convert to the extended values unless greater resolution is required. Programmable Filter Coefficients and Equations The frequency domain transfer function equation for the X and R filters is:
hf = h0 + h1 z h5z
-5 -1
Note: AmMAPTM software, which calculates X and R filter coefficients, is available from Advanced Micro Devices. Contact your local AMD Sales Office for more information.
+ h2 z
-6
-2
+ h3z
-7
-3
+ h4 z
-4
+
Test Facilities Three capabilities are provided for MAP operation verification.
+ h6 z
+ h7 z
where: z = cos (wT) + i V sin(wT) i = (-1) 1/2 w = frequency of input signal in Hz * 2pi T = sample period in seconds (0.125 ms) hj (j = 0,1,...7) = user-defined coefficients. Each hj coefficient is defined by the following equation:
hj = A3 { 1 + A2 [ 1 + A ( 1 + A0 ) ] }
MAP Analog Loopback
Signals sent in on AINA or AINB may be sent back out to EAR1/EAR2 or LS1/LS2 by looping the MAP path in the MUX. The MUX should be set up for Ba-to-Ba loopback by writing 33H to MCR1, MCR2, or MCR3. No other MUX connections overriding Ba-to-Ba should be programmed. This test allows the MAP analog and digital to be tested using a local signal source.
MAP Digital Loopback 1
This loopback mode connects the interpolator output to the decimator input in place of the ADC output. This mode allows verification from the S Interface or micro-
AM79C30A/32A Data Sheet
31
processor that the MAP digital circuitry is functional. Note that the digital patterns received after loopback will not be identical to the transmitted patterns. The D-D gain is approximately 2.5 dB.
MAP Digital Loopback 2
This loopback mode connects the analog D/A output path to the analog A/D input path, internal to the DSC circuit. The EAR and LS outputs and both AIN inputs will be disabled. This mode allows verification from the S Interface or microprocessor that the MAP analog and digital circuitry are functional. The digital patterns received after loopback will not be identical to the transmitted patterns. The bits in the MAP mode Register define the enable/disable options for the various MAP configurations as follows. MAP Registers The MAP contains the programmable registers found in Table 31.
Following reset, the MAP registers FTGR, MMR1, MMR2, MMR3, STRA, and STRF all default to 00 hex. All other MAP registers are not affected by reset and must be programmed by the microprocessor before being enabled. When the registers are disabled, or after reset, the MAP will have the response shown in Table 32.
Table 32.
Filter X filter R filter GX filter GR filter GER filter Sidetone gain
Default Values
Default Response Disabled (0 dB, Flat) Disabled (0 dB, Flat) Disabled (0 dB, Gain) Disabled (0 dB, Gain) Disabled (0 dB, Gain) Disabled (-18 dB, Gain)
Table 31.
MAP Register X-filter Coefficient Register
Map Registers
Bytes 16 16 2 2 2 2 2 2 1 1 1 1 1 Mnemonic X R GX GR GER STGR FTGR ATGR MMR STRA STRF PEAKX PEAKR
R-filter Coefficient Register GX-Gain Coefficient Register GR-Gain Coefficient Register GER-Gain Coefficient Register Sidetone-Gain Coefficient Register Frequency Tone Generator Register Amplitude Tone Generator Register MAP mode Registers (3) Secondary Tone Ringer Amplitude Reg Secondary Tone Ringer Frequency Reg Transmit Peak Register Receive Peak Register
Note: It is necessary to complete any transfers to the multi-byte MAP registers. For instance, a total of 16 bytes must be transferred to update the X filter.
32
AM79C30A/32A Data Sheet
MAP Mode Register 1 -- (MMR1) -- Read/Write Address = Indirect 69H
Table 33.
Bit 0 1 2 3 4 5 6 7 Logical 1 A-Law GX coefficient loaded from register GR coefficient loaded from register GER coefficient loaded from register X coefficient loaded from register R coefficient loaded from register
Map Mode Register 1
Logical 0 (Default Value) -Law GX bypassed; gain = 0 dB GR bypassed; gain = 0 dB GER bypassed; gain = 0 dB X bypassed; response = flat R bypassed; response = flat STG gain = -18 dB* Digital loopback #1 at MAP disabled
Sidetone gain coefficient loaded from register Digital loopback #1 at MAP enabled
Note: *To remove the sidetone path completely, it is necessary to enable the STG function by setting MMR1 bit 6 to 1, and program the STGR coefficient to 9008 (hex).34
MAP Mode Register 2 -- (MMR2) -- Read/Write Address = Indirect 6AH
Table 34.
Bit 0 1 2 3 4 5 6 7 Logical 1 AINB selected LS1/LS2 selected DTMF enabled Tone generator enabled Tone ringer enabled High pass filter disabled ADC auto-zero function disabled Reserved, must be Logical 0
Map Mode Register 2
Logical 0 (Default Mode) AINA selected EAR1/EAR2 selected DTMF disabled Tone generator disabled Tone ringer disabled High pass filter enabled ADC auto-zero function enabled Reserved, must be Logical 0
Note: For most applications, MMR2 bits 5 and 6 should always be written to logical 0. This enables the 50-60 Hz rejection filter and the internal offset cancellation circuits to operate normally. They can both be disabled when system or test conditions require the transmission of DC or low frequency signals.
AM79C30A/32A Data Sheet
33
Map Mode Register 3 -- (MMR3) -- Read/Write Address Indirect 6CH
Table 35.
Bit 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 X 0 0 0 0 1 1 1 1 X X X X X X X X 5 X 0 0 1 1 0 0 1 1 X X X X X X X X 4 X 0 1 0 1 0 1 0 1 X X X X X X X X 3 X X X X X X X X X 1 0 X X X X X X 2 X X X X X X X X X X X 1 0 X X X X 1 X X X X X X X X X X X X X 1 0 X X 0 Function
Map Mode Register 3
X Bit 7 Reserved, must be written to 0 X 0-dB pre-amplifier gain, 1.250-V maximum peak input voltage X +6-dB pre-amplifier gain, 0.625-V maximum peak input voltage X +12-dB pre-amplifier gain, 0.312-V maximum peak input voltage X +18-dB pre-amplifier gain, 0.156-V maximum peak input voltage X +24-dB pre-amplifier gain, 0.078-V maximum peak input voltage X Reserved; undefined X Reserved; undefined X Reserved; undefined X MUTE ON, AINA and AINB inputs disabled X MUTE OFF, AINA or AINB enabled X Digital Loopback 2 enabled; D/A output looped to A/D input; EAR, LS, and AIN pin disabled X Digital Loopback 2 disabled X EAR and LS simultaneously enabled X EAR or LS enabled by MMR2 bit 1 1 0 Secondary Tone Ringer enabled Secondary Tone Ringer disabled
Secondary Tone Ringer Amplitude Register -- (STRA) -- Read/Write Address = Indirect 6DH
Table 36.
Bit 7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X 6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Secondary Tone Ringer Amplitude
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Peak-to-Peak Output Voltage Silent Reserved Reserved Reserved Reserved Reserved 0.22 V 0.31 V 0.44 V 0.62 V 0.88 V 1.25 V 1.77 V 2.50 V 3.53 V 5.00 V Bits 0-3 Reserved; must be written to 0 -27 dB -24 dB -21 dB -18 dB -15 dB -12 dB -9 dB -6 dB -3 dB 0 dB 0.25 mW 0.5 mW 1.0 mW 2.0 mW 4.0 mW 8.0 mW 16.0 mW 31.25 mW 62.5 mW 125.0 mW Relative Output Approximate Power into 50 ohms
34
AM79C30A/32A Data Sheet
Secondary Tone Ringer Frequency Register (STRF), Read/Write; Address = Indirect 6EH STRF is a Read/Write register controlling the frequency of the secondary tone ringer. Hex codes 7F and 00 are reserved and should not be used. The coefficients are defined in Table 37. Table 37.
Counter Value 3F 1F 0F 87 43 A1 D0 E8 F4 7A 3D 1E 8F C7 63 B1 58 2C 16 0B 05 02 01 80 40 20 10 88 C4 E2 71 38 1C 8E 47 23 91 48 A4 D2 E9 74 3A 1D 0E 07 03 81 C0 60 30 98 4C 26 93 49 Frequency (Hz) Reserved Reserved 12000.0 9600.0 8000.0 6857.1 6000.0 5333.3 4800.0 4363.6 4000.0 3692.3 3428.6 3200.0 3000.0 2823.5 2666.7 2526.3 2400.0 2285.7 2181.8 2087.0 2000.0 1920.0 1846.2 1777.8 1714.3 1655.2 1600.0 1548.4 1500.0 1454.6 1411.8 1371.4 1333.3 1297.3 1263.2 1230.8 1200.0 1170.7 1142.9 1116.3 1090.9 1066.7 1043.5 1021.3 1000.0 979.6 960.0 941.2 923.1 905.7 888.9 872.7 857.1 842.1 Counter Value 3B 9D 4E 27 13 09 04 82 41 A0 50 A8 D4 6A B5 DA 6D B6 5B AD D6 6B 35 9A 4D A6 D3 69 34 1A 0D 86 C3 E1 F0 F8 7C BE DF 6F B7 DB ED F6 7B BD 5E AF D7 EB 75 BA 5D 2E 17 8B
Frequencies for Secondary Tone Ringer
Frequency (Hz) 727.3 716.4 705.9 695.7 685.7 676.1 666.7 657.5 648.7 640.0 631.6 623.4 615.4 607.6 600.0 592.6 585.4 578.3 571.4 564.7 558.1 551.7 545.5 539.3 533.3 527.5 521.7 516.1 510.6 505.3 500.0 494.9 489.8 484.9 480.0 475.3 470.6 466.0 461.5 457.1 452.8 448.6 444.4 440.4 436.4 432.4 428.6 424.8 421.1 417.4 413.8 410.3 406.8 403.4 400.0 396.7 Counter Value D8 6C 36 1B 8D C6 E3 F1 78 3C 9E CF E7 73 39 9C CE 67 33 19 8C 46 A3 D1 68 B4 5A 2D 96 4B 25 12 89 44 A2 51 28 94 4A A5 52 A9 54 2A 95 CA E5 72 B9 DC EE 77 BB DD 6E 37 Frequency (Hz) 369.2 366.4 363.6 360.9 358.2 355.6 352.9 350.4 347.8 345.3 342.9 340.4 338.0 335.7 333.3 331.0 328.8 326.5 324.3 322.2 320.0 317.9 315.8 313.7 311.7 308.7 307.7 305.7 303.8 301.9 300.0 298.1 296.3 294.5 292.7 290.9 289.2 287.4 285.7 284.0 282.4 280.7 279.1 277.5 275.9 274.3 272.7 271.2 269.7 268.2 266.7 265.2 263.7 262.3 260.9 259.5 Counter Value F7 FB FD 7E BF 5F 2F 97 CB 65 32 99 CC 66 B3 59 AC 56 2B 15 8A C5 62 31 18 0C 06 83 C1 E0 70 B8 5C AE 57 AB 55 AA D5 EA F5 FA 7D 3E 9F 4F A7 53 29 14 0A 85 42 21 90 C8 Frequency (Hz) 247.4 246.2 244.9 243.7 242.4 241.2 240.0 238.8 237.6 236.5 235.3 234.2 233.0 231.9 230.8 229.7 228.6 227.5 226.4 225.4 224.3 223.3 222.2 221.2 220.2 219.2 218.2 217.2 216.2 215.3 214.3 213.3 212.4 211.5 210.5 209.6 208.7 207.8 206.9 206.0 205.1 204.3 203.4 202.5 201.7 200.8 200.0 199.2 198.4 197.5 196.7 195.9 195.1 194.3 193.6 192.8
AM79C30A/32A Data Sheet
35
Table 37.
Counter Value 24 92 C9 64 B2 D9 EC 76 Frequency (Hz) 827.6 813.6 800.0 786.9 774.2 761.9 150.0 738.5
Frequencies for Secondary Tone Ringer (Continued)
Frequency (Hz) 393.4 390.2 387.1 384.0 381.0 378.0 375.0 372.1 Counter Value 9B CD E6 F3 79 BC DE EF Frequency (Hz) 258.1 256.7 255.3 254.0 252.6 251.3 250.0 248.7 Counter Value E4 F2 F9 FC FE FF Frequency (Hz) 192.0 191.2 190.5 189.7 189.0 188.2
Counter Value 45 22 11 0-8 84 C2 61 B0
Data Link Controller (DLC)
Overview A 16-Kbit/s D-channel is time-multiplexed within the frame structure of the S Interface. The data carried by the D channel is encoded using the Link Access Protocol D-channel (LAPD) format shown in Figure 4. The D channel can be used to carry either end-to-end signaling or low-speed packet data. Further information concerning LAPD protocol can be found in the CCITT recommendations. The LIU controls the multiplexing and demultiplexing of the D-channel data between the S Interface and the DLC. The DLC performs processing of Level-1 and partial Level-2 LAPD protocol, including flag detection and generation, zero deletion and insertion, Frame Check Sequence (FCS) processing for error detection, and some addressing capability. High level protocol processing is done by the external microprocessor. The microprocessor may process the address field in the LAPD frame depending on the programmed state of the DLC. The status of the DLC is held in the status registers and relevant interrupts are generated under user program control. In addition to transmit and receive data FIFOs, the DLC contains a 16-bit pseudo-random number generator (RNG) used in the CCITT D-channel address allocation procedure.
last byte of the aborted packet is read from the D-channel Receive buffer. The Receive-Abort interrupt can be masked by setting DMR2 bit 0 to a logical 0. With the exception of the Packet-Reception-in-Progress bit, no other bits associated with packet reception are updated after a receive packet abort. The receive frame can be aborted at any time by setting INIT bit 6 to logical 1. Similarly, the transmit frame can be aborted by setting INIT bit 7 to a logical 1. When the transmit frame is aborted, seven consecutive 1s are transmitted on the S Interface followed by a logical 0, and DSR1 bit 7 is set to a logical 1. Seven consecutive 1s followed by a 0 will continue to be transmitted as long as INIT bit 7 is set to 1. DSR1 bit 7 will be set after each sequence of seven consecutive 1s followed by 0. Level-2 Frame Structure The D-channel Level-2 frame structure conforms to one of the formats shown in Figure 4. All frames start and end with the flag sequence consisting of one 0 followed by six 1s followed by one 0. A packet consists of a Level-2 frame minus the flag bytes. The LSB is transmitted first for all bytes except the FCS. The flag preceding a packet is defined as the opening flag. Therefore, the byte following an opening flag, by definition, cannot be an abort or another flag. A closing flag is defined as a flag that terminates a packet. This flag can be followed by another flag(s), interframe fill consisting of all 1s or flags, or the address field of the next packet. In the latter case, the closing flag of one packet is the opening flag of the next packet. The DLC receiver can recognize interframe fill consisting of logical 1s or flags. The DLC transmitter follows the closing flag with interframe fill consisting of all 1s (mark Idle) if DMR4 bit 4 is set to a logical 0, or all 0s (flag Idle) if DMR4 bit 4 is set to a logical 1. CCITT I-series D-channel access protocol specifies use of mark Idle. When a collision is detected (mismatch of a D and E bit), a complete frame must be retransmitted. For transfer across the S Interface, the S-Interface frame structure is impressed upon the D-channel frame structure (LAPD). Zero Insertion/Deletion When transmitting, the DLC examines the frame content between the opening and closing flags. To ensure
D-channel Processing
Random Number Generator (RNG) The RNG is accessible by the microprocessor and operates in the following manner. On the Low-to-High transition of the reset signal, the RNG is cleared, then started. The RNG stops when the LSB or MSB of the 16-bit counter is read by the microprocessor, or when the MSB is loaded by the microprocessor. Writing to the MSB of the counter loads this byte but does not start the RNG. The RNG starts when the LSB of the counter is loaded by the microprocessor. Frame Abort The DLC aborts an incoming D-channel frame when seven contiguous logical 1s are received. When this occurs, an End-of-Receive-Packet interrupt is issued to the processor. DER bit 0 is set to a logical 1 when the
36
AM79C30A/32A Data Sheet
that a flag sequence is not repeated within the flag boundaries of the frame, a logical 0 bit is automatically inserted after each sequence of five contiguous logical 1s. When receiving, the DLC examines the frame content between the opening and closing flags and automatically discards the first logical 0 which directly follows five contiguous logical 1s. D-Channel Address Recognition The address field, shown in Figure 4, allows for three types of addresses: 1. 1-byte address signified by the LSB of the first address byte being set to a logical 1 2. 2-byte address signified by the LSB of the first address byte being set to a logical 0, and the LSB of the second address byte being set to a logical 1 3. More than 2-byte address signified by the LSB of both the first and second address bytes being set to a logical 0
In the case of the LAPD operating environments, the address is a 2-byte address where the first byte is analogous to the Service Access Point Identifier (SAPI) and the second byte is analogous to the Terminal Endpoint Identifier (TEI) as defined by the CCITT recommendations. The DLC is able to recognize D-channel addresses of all of the three types outlined above. Note that only the first two bytes of a more than 2-byte address can be checked by the DLC. There are four First Received Byte Address Registers (FRARs) which hold the values used to match against the first byte of the incoming address. Similarly, there are four Second Received Byte Address Registers (SRARs) which hold the values used to match against the second byte of the incoming address. FRAR4 defaults to FE hex; SRAR4 defaults to FF hex. This default is analogous to the broadcast address defined by the CCITT recommendations. The type of address recognition which is enabled is shown in Table 38
1
2
3
4
5
6
7
8 OCTET 2
EA =0 C/R
SAPI
EA =1
TEI
OCTET 3
FLAG 01111110 OCTET FLAG 01111110 OCTET 1 1
ADDRESS 16 bits 2,3 ADDRESS 16 bits 2,3
CONTROL 8 bits 4
FCS 16 bits 5,6
FLAG 01111110 7 FCS 16 bits N-1 FLAG 01111110 N
09893H-4
Minimum Packet
CONTROL 8 bits 4
INFORMATION N bits 5...
General
Notes: EA = Address Field Extension bit SAPI = Service Access Point Identifier FCS = Frame Check Sequence
C/R = Command/Response Field bit TEI = Terminal Endpoint Identifier
Figure 4.
Level-2 Frame Structure Formats
AM79C30A/32A Data Sheet
37
Table 38.
DMR4 Bit 7 0 Bit 5 1 7 X X 1 1 1 X X X 1 X 0 X X X 1 X X 0 6 X 1 X X X 1 X X X 1 X 0 DMR1 Bits 5 X X X X 1 X X X 1 X X 0 4 1 X X 1 X X X 1 X X X 0
.Address Recognition
Type of address recognition FRAR1 FRAR3 FRAR4 SRAR1 SRAR2 SRAR3 SRAR4 FRAR1:SRAR1 FRAR2:SRAR2 FRAR3:SRAR3 FRAR4:SRAR4 Address recognition disabled 2-byte address Second received byte-only address First received byte-only address
If DMR4 bit 6 is set to a logical 0, bit 1 of the FRARs is ignored when matching the first incoming address byte. If DMR4 bit 6 is set to a logical 1, all bits of the FRARs are used when matching the first incoming address byte. FRAR bit 1 is analogous to the C/R bit defined by the CCITT recommendations. The address recognition mechanism for the four FRAR/SRAR addresses can be individually enabled/disabled via DMR1 bits 4-7. First Received Byte-Only Address Recognition If DMR4 bit 5 is set to a logical 1 and DMR4 bit 7 is set to a logical 0, only the first byte of the incoming address is compared with the values stored in the enabled FRARs. An interrupt is generated if there is an address match and the Valid Address interrupt is enabled. If the address matches, the packet will be received. Second Received Byte-Only Address Recognition If DMR4 bits 5 and 7 are set to a logical 1, the DLC compares only the value in the second byte of the incoming address with values stored in the enabled SRARs. An interrupt is generated if there is an address match and the Valid Address interrupt is enabled. If the address matches, the packet will be received. 2-Byte Address Recognition If DMR4 bit 5 is set to a logical 0, the first byte of the incoming address is compared with the values stored in the enabled FRARs, and the second byte of the incoming address is compared with the value stored in the corresponding SRAR. An interrupt is generated if a match is found for both incoming address bytes with a FRAR/SRAR pair and the Valid Address interrupt is enabled. If the address matches, the packet will be received. Disabling Address Recognition If DMR1 bits 4, 5, 6, and 7 are all set to logical 0, all address recognition is disabled and all addresses are rec38
ognized and received. In this case, the AM79C30A/32A receives the first two bytes following the opening flag (the incoming address), and then issues an End of Address interrupt if the End of Address interrupt is enabled.
DLC Operation
DLC Transmit and Receive FIFOs The DLC Transmit and Receive FIFOs may be configured to the Normal or Extended mode of operation.Normal mode is fully backwards compatible with the Revision D or prior DSC circuit, and is activated upon RESET or if EFCR bit 0 is programmed to logical 0. In Normal mode the Transmit and Receive FIFOs are each 8 bytes in length. The Extended mode of FIFO operation may be activated by programming EFCR bit 0 to a logical 1, increasing the depth of the Transmit and Receive FIFOs to 16 bytes and 32 bytes, respectively. The setting of EFCR bit 0 to logical 1 also alters the available programmable FIFO threshold values set by DMR4 bits 2 and 3. Receiving D-Channel Packets The receiver controls the flow of D-channel data to the D-channel Receive buffer and the termination of a receive packet. Up to two packets can be contained in the D-channel Receive buffer. After receiving an opening flag (a bit sequence of 01111110) and one byte of data which is not an abort or flag on the D channel, the DLC sets the Packet-Reception-in-Progress status bit (bit 2) in D-channel Status Register 1 (DSR1). The DLC then receives the first two bytes (the two address bytes). If address recognition is enabled, the AM79C30A/32A issues a Valid Address interrupt if a match between the programmed values and the received address is detected. If no match is detected and address recognition is enabled, the DLC ignores the packet. If address recognition is
AM79C30A/32A Data Sheet
disabled, the AM79C30A/32A receives the first two bytes, issues an End of Address interrupt, and receives the packet. Both a Valid Address and an End of Address interrupt set Interrupt Register bit 2 to a logical 1 and bit 0 of the D-channel Status Register 1 (DSR1) to a logical 1. The Valid Address/End of Address interrupt can be disabled via DMR3 bit 0. There is an internal 3-byte delay which holds the first of the D-channel address bytes until the interrupt has been issued. Note that the incoming address bytes cannot be read however, until the D-channel Receive Byte Available or D-channel Receive Threshold interrupt is set. After the address is received, the DLC continues to receive D-channel bytes into the D-channel Receive buffer FIFO. The DLC issues an interrupt when data is available in the D-channel Receive buffer. This interrupt can be disabled by setting DMR3 bit 3 to a logical 0. The DLC also issues an interrupt when the receive threshold set in DMR4 is reached. This interrupt can be disabled by programming a logical 0 into DMR1 bit 1. By polling, the microprocessor can then read the D-channel bytes. The 3-byte delay incurred during address recognition is maintained. Therefore, the DLC receives the Frame Check Sequence (FCS) before issuing an interrupt to signal the last byte of the packet has been received and appropriate status bits have been updated. If DMR3 bit 7 is set, the two FCS bytes at the end of the packet are transferred into the D-channel Receive buffer along with the data. The DLC issues an interrupt when the last byte of the packet is read from the DCRB. This interrupt can be disabled by setting DMR3 bit 2 to a logical 0. After the FCS is received, the DLC receiver detects the closing flag (a bit sequence of 01111110) and then terminates the packet by issuing an End Of Receive Packet interrupt (bit 1 of DSR1) and returns to looking for opening flags. The DLC also terminates the packet when an abort, an overflow, or overrun error condition is detected. The End Of Receive Packet interrupt can be disabled by setting DMR1 bit 3 to a logical 0. The D-channel Receive Byte Count Register (DRCR) is a 16-bit wide, two-word deep FIFO that is used to record the number of bytes in the incoming D-channel packets. Each count is terminated by an end-of-packet condition. Thus, the DRCR informs the microprocessor of the number of bytes, including the address bytes, which have been received. The counter is updated when the last byte of a packet is placed in the D-channel Receive buffer. When the FCS bytes are included in the data transferred to the D-channel Receive buffer, the FCS bytes are included in the byte count; if the FCS bytes are not included in the transfer, they are not included in the byte count. The opening flag and closing flag are not included in the byte count.
The D-channel Error and Address Status Registers are also double buffered. Reading the last byte of a packet causes the DER byte to propagate to the output of the FIFO and updates the D-channel Status and Interrupt Registers accordingly. Reading the MSB of the DRCR causes the next count and associated ASR byte to propagate to the output of the FIFOs and updates the D-channel Status and Interrupt Registers accordingly. For this reason it is important to read ASR, DER, and DSR1 prior to reading the DRCR. When a receive error occurs, an End-of-Packet interrupt is generated and the packet is terminated. When the last byte of the associated packet is read from the D-channel Receive buffer, the appropriate DER bits are set and an error interrupt is generated. All error interrupts can be individually masked by setting the corresponding bits in DMR2 to a logical 0. There is one 16-bit D-channel Receive Byte Limit Register (DRLR). The received byte count is compared with the DRLR. When the byte count of the currently received D-channel packet exceeds the limit value, a receiver overflow is detected, the packet is terminated, and an End-of-Packet interrupt is issued. D-channel Error Register (DER) bit 4 is set to a logical 1 and an overflow interrupt issued when the last byte of the associated packet is read from the D-channel Receive buffer. The Overflow Error interrupt can be masked by setting DMR2 bit 4 to a logical 0. The minimum packet length is 5 bytes for a 2-byte address packet (not including flags). If the packet length is less than the above, an interrupt is issued and DER bit 5 is set to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer. The error interrupt can be masked by setting DMR2 bit 5 to a logical 0. If packet reception is in progress and the D-channel Receive buffer is full, the microprocessor has a maximum of 425 s to respond to the D-channel Receive Data Available interrupt. If the microprocessor fails to do so, then an overrun error occurs when the data byte is overwritten. When this happens, the packet is terminated. DER bit 6 is set to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer. The Overrun Error interrupt can be masked by setting DMR2 bit 6 to logical 0. Error indication is given if two packets have been received and not serviced by the user and a third packet is received via DSR2 bit 2. When this error occurs, the third packet is terminated (not received). Error indication is given for a receiver abort (the reception of seven contiguous 1s) by DER bit 0. If the number of bits received between two flags is not an integer multiple of eight (if the received packet does not contain an integral number of bytes), DER bit 1 is
AM79C30A/32A Data Sheet
39
set and an interrupt is generated when the last byte of the associated packet is read from the D-channel Receive buffer. The incoming bit stream (including FCS) is run through the FCS generation and compare block. Upon receipt of the closing flag, the result is checked and must be (MSB first) 0001110100001111. Any other pattern indicates an FCS error, and DER bit 3 is set to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer. The DLC receiver does not assume the packet to be byte-aligned. The architecture supports shared flags between packets, interframe fill consisting of logical 1s (Mark idle), and interframe fill consisting of flags (Flag idle). Mark idle is defined as at least 15 or more contiguous 1s. Flag idle is defined as more than two consecutive flag characters, not including a closing flag. DSR2 bit 5 is set to a logical 1 while Mark idle is being detected. DSR2 bit 6 is set to a logical 1 while Flag idle is being detected. The receiver D-channel packet can be aborted at any time during reception by setting INIT bit 6. Transmitting D-Channel Packets The DLC Transmitter is activated when the MSB (second byte) of the 16-bit D-channel Transmit Byte Count Register (DTCR) is loaded by the microprocessor. Next, the LIU starts counting the number of consecutive 1s on the E-channel until the number of 1s defined by the LIU priority mechanism is detected. After the sequence of 1s, the DLC transmitter will begin packet transmission. Address bytes for a transmit packet can be handled in two ways: they can be loaded into the transmit buffer or loaded into the Transmit Address Register (TAR). There is one 16-bit TAR which can be loaded by the microprocessor. The bytes loaded into the TAR are transmitted LSB first followed by MSB. For LAPD operation, the LSB contains the SAPI, and the MSB contains TEI. This 16-bit address (loaded LSB first) is transmitted within the address field of the D-channel packet if enabled by setting DMR1 bit 2 to a logical 1. If the TAR is enabled, the DTCR should be loaded with the number of bytes to be transmitted excluding the address, flags, and FCS. If the TAR is disabled, the DTCR should be loaded with the number of bytes to be transmitted excluding the flags and FCS, and the microprocessor must load the address to be transmitted as the first two bytes of the D-channel packet data. The DLC issues an interrupt when a position is avail-able in the D-channel Transmit buffer. This interrupt can be disabled by setting DMR3 bit 5 to a logical 0. The DLC also issues an interrupt to the microprocessor to request D-channel data bytes when the D-chan-
nel Transmit buffer empties to the threshold specified in the D-channel FIFO mode register. This interrupt can be disabled by setting DMR1 bit 0 to a logical 0. If the D-channel Transmit buffer is empty, the microprocessor has up to 375 ms to respond to the D-channel transmit buffer interrupt. If the microprocessor fails to load the data bytes in this time frame, an underrun interrupt is generated in DER bit 7, and packet transmission is terminated with a transmitted abort. The Underrun interrupt can be masked by setting DMR2 bit 7 to a logical 0. Transmission is also terminated when a collision is detected or LIU loss of synchronization occurs. The D-channel Transmit Byte Count Register is decremented each time a byte of data is transferred from the D-channel Transmit buffer to the DLC. The count represents the number of bytes left to be transferred, excluding the FCS and flags. If the transmit abort bit (INIT bit 7) is set, the transmit byte count is frozen and indicates the number of bytes left to transfer, not the number of bytes transmitted. The last byte of the packet is determined by the D-channel Transmit Byte Count decrementing to zero. When this occurs, DSR2 bit 3 is set to a logical 1. After the last byte of the packet is transmitted, the DLC adds the FCS and closing flag. Then the DLC issues an interrupt (bit 6 of DSR1) to signify the end of the packet transmission. This interrupt can be masked by setting DMR3 bit 1 to a logical 0, and is reset either by reading DSR1 or when the D-channel Transmit Byte Count Register is loaded for the next packet. Once the D-channel Transmit Byte Count has decremented to 0, a second packet may be loaded into the D-channel Transmit FIFO. If the MSB of the D-channel Transmit Byte Count Register is loaded prior to the end-of-transmit packet interrupt, the second packet is transmitted back-to-back with the previous packet. The End-of-Transmit Packet interrupt is not set between the two packets. If the MSB of the D-channel Transmit Byte Count Register is loaded after the end-of-packet interrupt, the second packet is transmitted once the LIU priority mechanism has been resatisfied. Collision Detection The Network Terminator echoes the transmitted D-channel data back to the DLC in the E-channel bits of the S-interface frame. If there is a difference between the data transmitted and the data echoed back, a collision has occurred. The DLC alerts the microprocessor to this event by asserting the interrupt line (INT) and setting DER bit 2. If a collision occurs during the transmission of an abort sequence, the interrupt is still issued. The collision detect interrupt can be masked by setting DMR2 bit 2 to a logical 0.
40
AM79C30A/32A Data Sheet
D-Channel Receive and Transmit Errors
Non-Integer Number of Bytes
A non-integer number of bytes occurs when the number of D-channel bits received between opening and closing flags is not divisible by eight. If a received packet consists of a non-integer number of bytes, the DLC sets bit 1 in the D-channel Error Register (DER) to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer.
Underflow
If a received D-channel (including FCS) packet is less than 5 bytes for a 2-byte address packet, an underflow error condition occurs, and the DLC sets DER bit 5 to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer.
Overrun
A D-channel overrun error occurs when the receiver buffer is full, and another byte is received. This can happen if the D-channel Receive buffer fills, and is not read within 425 s. When this error occurs, the DLC sets DER bit 6 to a logical 1 and terminates the packet.
Frame Check Sequence Error
If a received packet, including its 16-bit Frame Check Sequence, is not received perfectly, the DLC sets DER bit 3 to a logical 1 when the last byte of the associated packet is read from the Receive buffer.
Underrun
A D-channel underrun error occurs when an empty D-channel buffer is transmitted. This can happen if the D-channel Transmit buffer is not loaded within 375 s of the D-channel Transmit buffer Empty interrupt being asserted (IR bit 0). When this error occurs, the DLC sets DER bit 7 to a logical 1 and terminates the packet.
Receive Packet Abort
If seven contiguous 1s are received while receiving a packet, the packet will be terminated. DER bit 0 will be set to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer.
Overflow
Overflow occurs when the total number of D-channel bytes within a packet (including, only when enabled, the Frame Check Sequence bytes) exceeds the limit contained in the D-channel Receive Byte Limit Register. (See Receiving D-channel Packets section.) When overflow occurs, the DLC terminates the packet, and sets DER bit 4 to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer.
Receive Packet Lost
Receive Packet Lost occurs when two outstanding packets have been received and not serviced (the microprocessor has not read the DCRB register), and a third packet is received. When this error occurs, DSR2 bit 2 is set to a logical 1 and the incoming packet is terminated (not received).
DLC REGISTERS
The DLC contains the following registers.
Registers First Received Byte Address Registers Second Received Byte Address Registers Transmit Address Register (16-bit) D-channel Receive Byte Limit Register (16-bit) D-channel Receive Byte Count Register (16-bit) (2-word FIFO) D-channel Transmit Byte Count Register (16-bit) Random Number Generator Registers D-channel mode registers Address Status Register (2-byte FIFO) Extended FIFO Control Register D-channel Transmit buffer Register D-channel Receive buffer Register D-channel Status Register #1 D-channel Status Register #2 D-channel Error Register (2-byte FIFO) Number of Registers Mnemonic 4 4 1 1 1 1 2 4 1 1 -- -- 1 1 1 FRAR SRAR TAR DRLR DRCR DTCR RNGR DMR ASR EFCR DCTR DCRB DSR1 DSR2 DER
AM79C30A/32A Data Sheet
41
Transmit Address Register -- (TAR) -- Read/Write Address = Indirect 83H This register contains the address of the packet to be transmitted if the TAR bit is enabled (DMR1 bit 2). First Received Byte Address Register -- (FRAR1-FRAR4) -- Read/Write Address = Indirect FRAR1-FRAR3 = 81H, FRAR4 = 8CH These registers contain the value to match against the first byte of the incoming address. If DMR1 bits 4-7 are disabled, these registers are ignored. Second Received Byte Address Register -- (SRAR1-SRAR4) -- Read/Write Address = Indirect SRAR1-SRAR3 = 82H, SRAR4 = 8DH These registers contain the value to match against the first byte of the incoming address. If DMR1 bits 4-7 are disabled, these registers are ignored. D-Channel Receive Byte Count Register -- (DRCR) -- Read Address = Indirect 89H This register determines the maximum number of bytes in a received packet. D-Channel Receive Byte Limit Register -- (DRLR) -- Read/Write Address = Indirect 84H This register contains the total number of received bytes. D-Channel Transmit Byte Count Register -- (DTCR) -- Read/Write Address = Indirect 85H This register contains the total number of transferred bytes. Random Number Generator Register -- (RNGR1, RNGR2) -- Read/Write Address = Indirect RNGR1 = 8AH, RNGR2 = 8BH These registers control the operation of the Random Number Generator. When read, they display the random number generated by the chip. D-Channel Transmit Buffer Register -- (DCTB) --Write D-channel transmit FIFO. D-Channel Receive Buffer Register -- (DCRB) -- Read D-channel receive FIFO. D-Channel Mode Register 1 -- (DMR1) -- Read/Write Address = Indirect 86H DMR1 controls the enable/disable options for the DLC. It is under sole control of the microprocessor and does not generate any interrupts. DMR1 is defined in Table 39. Table 39.
Bit 0 1 2 3 4 5 6 7 Logical 1 Enable D-channel Receive Threshold interrupt (see IR bit 1) Enable Transmit Address Register Enable End of Receive Packet interrupt (see DSR1 bit 1) Enable FRAR1/SRAR1 Enable FRAR2/SRAR2 Enable FRAR3/SRAR3 Enable FRAR4/SRAR4
D-Channel Mode Register 1
Logical 0 Disable interrupt (default value) Disable Transmit Address Register (default value) Disable interrupt (default value) Disable FRAR1/SRAR1 (default value) Disable FRAR2/SRAR2 (default value) Disable FRAR3/SRAR3 (default value) Disable FRAR4/SRAR4
Enable D-channel Transmit Threshold interrupt (see IR bit 0) Disable interrupt (default value)
42
AM79C30A/32A Data Sheet
D-Channel Mode Register 2 -- (DMR2) -- Read/Write Address = Indirect 87H DMR2 is used to enable/disable the interrupts generated in the DER (see DER definition on page 41). DMR2 is controlled by the microprocessor and does not generate interrupts. DMR2 is defined in Table 40. Table 40.
Bit 0 1 2 3 4 5 6 7 Logical 1 Enable Receive Abort interrupt (see DER bit 0) Enable Non-integer Number of Bytes Received interrupt (see DER bit 1) Enable Collision Abort Detected interrupt (see DER bit 2) Enable FCS Error interrupt (see DER bit 3) Enable Overflow Error interrupt (see DER bit 4) Enable Underflow Error interrupt (see DER bit 5) Enable Overrun Error interrupt (see DER bit 6) Enable Underrun Error interrupt (see DER bit 7)
D-Channel Mode Register 2
Logical 0 (Default Value) Disable interrupt Disable interrupt Disable interrupt Disable interrupt Disable interrupt Disable interrupt Disable interrupt Disable interrupt
D-Channel Mode Register 3 -- (DMR3) -- Read/Write Address = Indirect 8EH
Table 41.
Bit 0 1 2 3 4 5 6 7 Logical 1
D-Channel Mode Register 3
Logical 0 (Default Value)
Enable Valid Address/End of Address interrupt (default value) (see DSR1 bit 0) Disable interrupt Enable End of Valid Transmit Packet interrupt (default value) (see DSR1 bit 6) Disable interrupt Enable Last Byte of Received Packet interrupt (see DSR2 bit 0) Enable Receive Byte Available interrupt (see DSR2 bit 1) Enable Last Byte Transmitted interrupt (see DSR2 bit 3) Enable Transmit buffer Available interrupt (see DSR2 bit 4) Enable Received Packet Lost interrupt (see DSR2 bit 2) Enable FCS transfer to FIFO Disable interrupt (default value) Disable interrupt (default value) Disable interrupt (default value) Disable interrupt (default value) Disable interrupt (default value) Disable FCS transfer to FIFO (default value)
AM79C30A/32A Data Sheet
43
D-Channel Mode Register 4 -- (DMR4) -- Read/Write Address = Indirect 8FH Table 42.
Bit 7 X X X X X X X X X X X 0 1 X X 6 X X X X X X X X X X X X X 0 1 5 X X X X X X X X X X 0 1 1 X X 4 X X X X X X X X 0 1 X X X X X 3 X X X X 0 0 1 1 X X X X X X X 2 X X X X 0 1 0 1 X X X X X X X 1 0 0 1 1 X X X X X X X X X X X 0 0 1 0 1 X X X X X X X X X X X Interframe Fill Address Recognition Transmitter Threshold
D-Channel Mode Register 4
Function 1 byte (EFCR bit 0 = 0) 1 byte (EFCR bit 0 = 1) 2 bytes (EFCR bit 0 = 0) 16 bytes (EFCR bit 0 = 1) 4 bytes (EFCR bit 0 = 0) 24 bytes (EFCR bit 0 = 1) 8 bytes (EFCR bit 0 = 0) 30 bytes (EFCR bit 0 = 1) 1 byte (EFCR bit 0 = 0) 1 byte (EFCR bit 0 = 1) 2 bytes (EFCR bit 0 = 0) 6 bytes (EFCR bit 0 = 1) 4 bytes (EFCR bit 0 = 0) 10 bytes (EFCR bit 0 = 1) 8 bytes (EFCR bit 0 = 0) 14 bytes (EFCR bit 1 = 1) Mark Idle (default value) Flag Idle 2-byte (default value) First Received Byte only Second Received Byte only Disable FRAR bit 1 compare (default value) Enable FRAR bit 1 compare
Control Receiver Threshold
C/R Bit Compare
Note: The receiver and transmitter thresholds can only be changed when the AM79C30A/32A is in Idle mode.
Address Status Register -- (ASR) -- Read Only Address = Indirect 91H Table 43.
Bit 0 1 2 3 4-7 Logical 1 FRAR1/SRAR1 address recognized FRAR2/SRAR2 address recognized FRAR3/SRAR3 address recognized FRAR4/SRAR4 address recognized Reserved
Address Status Register
Logical 0 (Default Value) No FRAR1/SRAR1 address match No FRAR2/SRAR2 address match No FRAR3/SRAR3 address match No FRAR4/SRAR4 address match Reserved
44
AM79C30A/32A Data Sheet
D-Channel Status Register 1 -- (DSR1) -- Read Only DSR1 has the format shown in Table 44. Table 44.
Bit 0 1 2 3 4 5 6 7 Logical 1 Valid Address (VA) if the address decode logic is enabled or End-of-Address (EOA) if the address decode logic is disabled End of receive packet Packet reception in progress Loopback in operation at AM79C30A/32A Loopback in operation at LIU D-channel back-off not in operation End of valid transmit packet Current transmit packet has been aborted
D-Channel Status Register 1
Logical 0 (Default Value) No valid address Not end of packet Packet not being received No loopback in operation at AM79C30A/32A No loopback in operation at LIU D-channel back-off in operation No end-of-transmit packet or no transmission No transmit packet abort
The DSR1 bits generate interrupts and are set/reset under the conditions shown in Table 45 (in addition to a hardware reset or Idle mode). Table 45.
Bit Generate Interrupt 0 1 2 3 4 5 6 7 Yes, if DMR3 bit 0 = 1 Yes, if DMR1 bit 3 = 1 No No No No Yes, if DMR3 bit 1 = 1 No Bit Set Two bytes after an opening flag if a VA is decoded or address recognition is disabled When a closing flag is received One byte after the opening flag of any packet, valid or not When the operation is in progress When the operation is in progress When the operation is in progress When the closing flag is transmitted
DSR1 Interrupts
Bit Reset When the microprocessor reads DSR1 or associated DRCR When the microprocessor reads DSR1 or associated DRCR When a flag or an abort is received When the operation is not in progress When the operation is not in progress When the operation is not in progress When the microprocessor reads DSR1 or when DTCR is loaded
When seven 1s and a 0 have been transmitted When the microprocessor reads DSR1 or when DTCR is loaded
AM79C30A/32A Data Sheet
45
D-Channel Status Register 2 -- (DSR2) -- Read Only DSR2 has the format illustrated in Table 46. Table 46.
Bit 0 1 2 3 4 5 6 7 Logical 1 Last byte of received packet Receive byte available Receive packet lost Last byte transmitted Transmit buffer available Mark idle detected (15 or more contiguous 1s)
D-Channel Status Register 2
Logical 0 (Default Value) Not last byte of received packet Receive byte not available Receive packet not lost Last byte not transmitted Transmit buffer not available* Mark idle not detected
Flag idle detected (more than two contiguous flags) Flag idle not detected Start of second received packet in FIFO Second packet not yet in FIFO
Note: *Following RESET, the Transmit buffer Available (bit 4) is set, producing a default value of 10H.
The DSR2 bits generate interrupts and are set/reset under the conditions shown in Table 47 (in addition to a hardware reset or Idle mode). Table 47.
Bit 0 1 2 3 4 5 6 7 Generate Interrupt Yes, if DMR3 bit 2 = 1 Yes, if DMR1 bit 3 = 1 Yes, if DMR3 bit 6 = 1 Yes, if DMR3 bit 4 = 1 Yes, if DMR3 bit 5 = 1 No No Yes, if EFCR bit 1 = 1 Bit Set When last byte of a received packet is read from the DCRB When DCRB contains one or more bytes of data When two outstanding packets are received and not serviced, and a third packet is received
DSR2 Interrupts
Bit Reset When the microprocessor reads the DSR2 When DCRB is empty When the microprocessor reads DSR2
When the last byte of a transmit packet is transferred from When the microprocessor reads the DCTB DSR2 When the DCTB is available to be loaded with a data byte When the DCTB is full When 15 contiguous one bits have been detected in the incoming D channel When the first zero bit is detected on the incoming D channel
When more than two contiguous flags are detected on the When a non-flag character is incoming D channels, not including a closing flag detected on the incoming D channel When start of second packet is in the receive FIFO When second receive packet is not present
46
AM79C30A/32A Data Sheet
D-Channel Error Register -- (DER) -- Read Only The DER has the format illustrated in Table 48. Table 48.
Bit 0 1 2 3 4 5 6 7 Logical 1 Received Packet Abort Non-integer number of bits have been received Collision Detected FCS Error Overflow Error Underflow Error Overrun Error Underrun Error
D-Channel Error Register
Logical 0 (Default Value) No abort received Integer number of bits received No error No error No error No error No error No error
DER bits 0, 1, 3, 4, 5, and 6 are set when the last byte of the associated packet is read from the D-channel Receive buffer. The DER bits generate interrupts and are set/reset under the conditions shown in Table 49 (in addition to a hardware reset). Table 49.
Bit Generates Interrupt 0 1 2 3 4 5 6 7 Bit Set
DER Interrupts
Bit Reset When the microprocessor reads the DER or associated DRCR When the microprocessor reads the DER or associated DRCR When the microprocessor reads the DER or when DTCR is loaded When the microprocessor reads the DER or associated DRCR When the microprocessor reads the DER or associated DRCR When the microprocessor reads the DER or associated DRCR When the microprocessor reads the DER or associated DRCR When the microprocessor reads the DER or when DTCR is loaded
Yes, if DMR2 bit 0 = 1 When seven consecutive 1s are received within a packet (DSR1 bit 2 = 1) Yes, if DMR2 bit 1 = 1 Upon error condition after closing flag has been received Yes, if DMR2 bit 2 = 1 See section on collision detection Yes, if DMR2 bit 3 = 1 If error occurs Yes, if DMR2 bit 4 = 1 If error occurs Yes, if DMR2 bit 5 = 1 If error occurs Yes, if DMR2 bit 6 = 1 If error occurs Yes, if DMR2 bit 7 = 1 If error occurs
Extended FIFO Control Register -- (EFCR) -- Read/Write Address = Indirect 92H
Bit 7 0 6 X 5 X 4 X 3 X 2 0 1 X 0 X Function Bits 7 and 2 reserved, must be written to 0 Bits 6-3 control attenuation of the analog sidetone path (ASTG) 0 0 0 0 0 1 X X X X 0 1 Start of Second Received Packet In FIFO interrupt disabled Start of Second Received Packet In FIFO interrupt enabled Normal mode of FIFO operation Extended mode of FIFO operation
See Table 20. 0 0 0 0 X X X X X X X X X X X X X X X X
AM79C30A/32A Data Sheet
47
Peripheral Port (PP)
Overview The purpose of the Peripheral Port is to allow external peripherals to be connected to the DSC/IDC circuit. There are two basic modes of operation, Serial Bus Port mode, and IOM-2 Terminal mode. Within IOM-2 Terminal mode, the DSC/IDC circuit may be configured as any combination of IOM-2 timing/control master or slave. The definition of the Peripheral Port pins depends on the operating mode of the port, as described in Table 50. Serial Bus Port (SBP) Mode The SBP mode of operation is backwards compatible with the Revision D DSC circuit serial port and is entered either following a device RESET or if programmed in PPCR1. In SBP mode, the SCLK output provides a 192-kHz 1X data clock of programmable polarity. The SBIN and SBOUT pins support three 8-bit serial data channels, designated Bd, Be, and Bf. The SFS output provides an 8-kHz serial frame sync pulse eight bit periods in width, coincident with the Bd channel. The SBP mode timing is illustrated in Figure 5.
Following a RESET, the SCLK and SFS outputs will default to a high-impedance state, which will be maintained until any MUX connection is programmed (or until the Peripheral Port is programmed to an IOM-2 mode). SCLK and SFS will remain in a high-impedance state if the Peripheral Port is explicitly disabled. The SCLK and SFS signals are synchronized to the received S-interface frame. If there is no S-interface frame synchronization, the SCLK and SFS signals will free-run at 192 kHz and 8 kHz respectively. If the DSC/IDC circuit is programmed to Idle mode, the SFS output is driven Low but SCLK continues to run. In Power-Down mode, both the SFS and SCLK outputs are high-impedance. IOM-2 Terminal Mode Overview The IOM-2 Interface standard encompasses both a Linecard mode and a Terminal mode. The Terminal mode was defined to provide four functions, as follows: 1. Connection of multiple Layer-2 devices to a Layer-1 device (in this case, the Layer-1 device is the S/T Interface LIU). Provision for the connection of non-IOM-2 devices is included. 2. Programming and control of Layer-1 or Layer-2 devices that do not have a microprocessor interface, for example, a U-interface transceiver.
Table 50.
Pin SBIN SBOUT SCLK SFS BCL/CH2STRB SBP On IN OUT OUT OUT OUT
Pin Operation versus Peripheral Port Modes
IOM-2 M Deactivated IN Z Low Low Low IOM-2 S* Bus IOM-2 S No IOM-2 S No IOM-2 S* Bus Reverse Bus Reverse Bus Reverse Reverse Deactivated Deactivated Activated Activated IN/OD OD/IN IN IN Z OD Z IN IN Z OD IN IN IN Z Z Z IN IN Z
Port IOM-2 M Disabled Activated Z Z Z Z Z IN OD OUT OUT OUT
IN = Input
OUT = Output
Z = High Impedance
OD = Open Drain Output
Note: *The AM79C30A is a non-Layer-1 component when operated in the Slave mode; however, it has a microprocessor interface. As a result, it is required to change the direction of its I/O pins at certain times in order to communicate with both the upstream Layer-1 device and any downstream peripheral devices. In the IOM-2 Slave mode, the direction of data flow is reversed with respect to the DSC circuit during Sub-frame 0 and during the deactivated state. The rule is that the upstream Layer-1 device only uses Sub-frame 0 and does not reverse its pins. Any non-Layer-1 component that does not contain a microprocessor interface (i.e., program by the DSC circuit over the Monitor channel in Sub-frame 1) uses Sub-frame 0 to talk to the Layer-1 device and Sub-frame 1 to talk to the DSC circuit. It does not reverse its pins.
48
AM79C30A/32A Data Sheet
52 s SCLK 192 kHz SBIN or SBOUT D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Bf B3 Bd SFS 41.7 s 125 s MSB LSB
Note: SBIN is sampled on the rising edge of SCLK. SBOUT is changed on the falling edge of SCLK.
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Figure 5.
Serial Bus Port Mode Timing * * One 16-kbits/s D channel for signaling and data packets. Two Command/Indicate channels, labeled C/I0, and C/I1, to provide status and command for devices connected via the monitor channels. The Command/Indicate channel in the first IOM-2 subframe consists of four bits, providing 16 states in each direction. In the second subframe the C/I channel is 6 bits, providing 64 states in each direction. Two 64-kbits/s intercommunication channels, labeled IC1 and IC2, to provide additional interdevice communications bandwidth.
3. Inter-chip communication between devices on the bus, for instance, data flow between the DSC circuit MAP and an external speech encryption device. 4. Connection of multiple DLCs to the D channel, including access arbitration. This function is referred to as the TIC channel. The IOM-2 Terminal mode bus consists of three IOM-2 subframes, each containing 32 bits. This 12-byte frame is repeated at 8 kHz, resulting in an aggregate data rate of 768 kbits/s. The frame structure is illustrated in Figure 7, and contains the following channels: * * Two 64-kbits/s data channels, labeled B1 and B2. Two device programming channels, labeled Monitor 0 and 1. Each channel has an associated pair of MX and MR handshake bits that control data flow.
*
All data transmitted on the IOM-2 Interface via the SBOUT pin is transmitted MSB first, with the exception of D-channel data, which is transmitted LSB first. The receiver operates in a compatible way via the SBIN pin.
SFS MR,MX SBIN/ B1 SBOUT IOM channel 0 IOM channel 1 IOM channel 2
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MR,MX IC2 MON1 C/I TIC
B2
MON0 D C/I
IC1
Figure 6.
IOM-2 Terminal Mode Frame Structure
AM79C30A/32A Data Sheet
49
DSC/IDC Circuit IOM-2 Terminal Mode Implementation
Data Channels
The B1 and B2 channels are physically the first two 8-bit time slots after the frame sync pulse. When making a MUX connection to these channels, IOM-2 channels B1 and B2 correspond to MUX channels Bd and Be, respectively. When in an IOM-2 mode, a MUX connection to channel Bf provides access to one of the two intercommunication channels as selected in PPCR1.
through the LIU. The D-channel data received from the S Interface is also output on the IOM-2 Interface. D-channel data received from the IOM-2 Interface is disregarded. If, however, TIC bus is enabled, the TIC bus control logic will arbitrate D-channel data flow between the S Interface and either the DLC or IOM-2 Interface based on TIC bus access procedures. When the Peripheral Port is configured as IOM-2 slave, the DLC will transmit and receive D-channel data to and from the IOM-2 Interface. This will be a dedicated path if the TIC bus feature is disabled, or with DLC access arbitrated according to TIC bus access procedures if the TIC bus feature is enabled. The LIU is not used in this situation, so there is no D-channel data flow between the DLC and LIU.
Command/Indicate Channels
The Peripheral Port supports the C/I channels of the first and second IOM-2 subframes. The Peripheral Port monitors these two channels, and generates an interrupt any time the received data changes and is stable for two frames. The received data is read from C/I Receive Data Register 0 or 1, and C/I transmit data is written to C/I Transmit Data Register 0 or 1. When the TIC bus feature is enabled, C/I0 transmit access to the IOM-2 Interface is controlled by CITDR0 bit 7, Bus Access Request.
Monitor Channels
Support for the two Monitor channels is provided on a one-at-a-time basis. A bit in Peripheral Port Control Register 1 selects which one of the two Monitor channels is utilized at any time.
TIC Bus
The IOM-2 TIC bus control bits reside in the last byte to the IOM-2 Terminal mode frame (channel 2, byte 4). The bits and their definitions are shown in Figure 7
D Channel
If the peripheral Port is configured as IOM-2 master with TIC bus disabled, the DLC will transmit and receive D-channel data to and from the S Interface
Data Upstream (output)
1
1
BAC TBA2 TBA1 TBA0
1
1
Data Downstream (input)
E
E
S/G
A/B
1
1
1
1
Notes: BAC bit (Bus Accessed): indication to other devices that the TIC bus is being accessed. When 0 the bus is accessed, when 1 it is free. This bit is driven to zero by the device that gets an address match on the TBA2-0 bits. TBA2-0 bits (TIC Bus Address): address bit used for arbitration of TIC bus control Assumes Open-Drain bus such that device with highest zero content in its address has the highest priority. Lowest priority address, which is also the default, is 111. E-bits (Echo): D-channel Echo bits from the S-bus. Will not be supported by the DSC. S/G bit (Stop/Go): used to indicate availability of the S-bus D-channel. When 0, the D-channel is clear for transmission. When 1, D-channel transmission should be halted. A/B bit (Available/Blocked): supplementary bit for D-channel control. 1 indicates D-channel available, 0 D-channel blocked. Optional, will not be supported by the DSC.
Figure 7.
TIC Bus Control Bits and Definitions
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AM79C30A/32A Data Sheet
MASTER Mode
DSC is the timing master (FSC and SCLK are outputs) and control master (can communicate with downstream devices). The configuration of timing master and control slave is covered within this mode. The presence of the TIC bus provides D and C/I0 access to all downstream devices. For control slave applications, the DSC can disable all IOM-2 channel 1 communications.
B1, B2, D, MON0, C/10, IC1, IC2, MON1, C/I1, S/G(out), TIC(in) SBOUT
upstream
DSC SBIN
DD Downstream #1 DU
DD Downstream #2 DU
downstream
Figure 8.
IOM-2 Master Mode Operation
AM79C30A/32A Data Sheet
51
SLAVE Mode -- Bus Reversal Enabled
DSC is the timing slave (FSC and SCLK are inputs) and control master (can communicate with other downstream devices via MONI and C/I1). D and C/I0 arbitration provided by TIC bus capability.
Utransceiver IC1, IC2, MON1, C/I1 DD DU
B1, B2, D, MON0, C/I0, S/G(in), TIC(out) SBOUT DSC SBIN
upstream
DD Downstream #1 DU
DD Downstream #2 DU
downstream
Figure 9. IOM-2 Slave Mode Operation with Bus Reversal
52
AM79C30A/32A Data Sheet
SLAVE Mode -- Bus Reversal Disabled
DSC is the timing slave (FSC and SCLK are inputs) and control master (cannot communicate with other downstream devices). D and C/I0 arbitration provided by TIC bus capability.
DSC Master SBOUT B1, B2, D, MON0, C/I0, IC1, IC2, MON1, C/I1, S/G(in), TIC(out) SBOUT DSC SBIN SBIN
upstream
DD Downstream #1 DU
DD Downstream #2 DU
downstream
Figure 10. IOM-2 Slave Mode Operation without Bus Reversal
AM79C30A/32A Data Sheet
53
Intelligent NT
Either Slave mode can be used to implement the Intelligent NT configuration. The diagram below depicts this configuration using DSC Slave mode with bus reversal disabled. The U-transceiver operates as the IOM-2 master device, programmed to TE mode and outputting at 1536-kHz DCL. The DSC indicates a D-channel request according to the TIC bus procedure using the BAC bit on the DU line (BAC=0). The S-transceiver surveys the received D channel and if it is idle, enables the DSC to send its D-channel frame to the U-transceiver on DU by driving S/G low on DD. The S-transceiver also sets its transmitted E-channel bits on the S-Interface to zero (inversion of received D bits) to prevent all connected TEs from transmitting data into the D-channel. When the DSC completes its D-channel transmission, it releases the TIC bus by setting BAC=1. The S-transceiver then mirrors the incoming D bits into the E-channel, thus behaving as a normal NT with transparent D-channel handling.
U-transceiver Master DOUT/DD B1, B2, D, MON0, C/I0, IC1, IC2, MON1, C/I1, S/G(in), TIC(out) SBOUT DSC SBIN DIN/DU
upstream
D-channel E-channel S-transceiver LT-S
DD DU
S Interface
downstream
Figure 11. IOM-2 Intelligent Configuration
54
AM79C30A/32A Data Sheet
Monitor Channel Procedures The Monitor channel operates on an event-driven basis; although data transfers on the bus are synchronized to the frame sync, the flow of data is controlled by a handshake procedure using the outgoing MX and incoming MR bits. Thus, the actual data rate is not fixed, but is dependent upon the response speed of transmitter and receiver. Figure 12 illustrates the sequence of events in the monitor handshake procedure.
byte of data has been transmitted, indicated by the Monitor Transmit Data Register being empty and the end-of-transmission (EOM) bit being set in PPCR1, outgoing MX is deactivated in response to incoming MR going inactive, and left inactive.
First Byte Reception
At the time the receiver sees the first byte, indicated by the inactive-to-active transition of incoming MX, outgoing MR is by definition inactive. Outgoing MR is activated in response to the activation of incoming MX, the data byte on the bus is loaded into the Monitor Receive Data Register, and a Monitor channel receive data available interrupt is generated. Outgoing MR remains active until the next byte is received or an end-of-message is detected (incoming MX held inactive for two or more frames).
Idle State
The outgoing MX and incoming MR bits held inactive for two or more frames indicates that the Monitor channel is Idle in the outgoing direction.
Start of Transmission
The PPCR1 register is programmed to select one of the two monitor channels. Data is then loaded into the monitor Transmit Data Register, causing the first data byte to be presented to the bus as well as an inactive-to-active transition of outgoing MX. The Monitor channel transmit buffer available interrupt is also generated when data is placed on the bus, indicating that the next data byte may be written to the buffer. Outgoing MX remains active, and the data is repeated until an inactive-to-active transition of the incoming MR is received.
Subsequent Reception
Data is received into the buffer on each falling edge of incoming MX, and a Monitor channel receive data available interrupt is generated. Note that the data was actually valid at the time incoming MX became inactive, one frame prior to becoming active. Outgoing MR is deactivated at the time data is read and reactivated one frame later. The reception of data is terminated by reception of an end-of-message indication, which is incoming MX remaining inactive for two or more frames.
Subsequent Transmission
Following detection of the first inactive-to-active transition of incoming MR, all following bytes to be transmitted will be presented to the bus coincident with an active-to-inactive transition of outgoing MX. The IOM-2 specification defines a general case (Figure 12a) in which the transmitter waits for an inactive-to-active transition of incoming MR, and a maximum speed case (Figure 12c) in which the transmitter achieves a higher transmission rate by anticipating the falling edge of incoming MR. The DSC/IDC circuit Monitor channel transmitter implements the maximum speed case as follows: the second byte is placed onto the bus at the start of the frame following the transition of incoming MR (High to Low), and a Monitor channel transmit buffer available interrupt is generated. Simultaneously, outgoing MX is returned inactive for one frame, then reactivated. Note that two frames of outgoing MX inactive signifies the end of a message. Outgoing MX and the data byte remain valid until incoming MR goes inactive. The next byte is transmitted during the next frame, meaning one frame after incoming MR goes inactive. In this manner, the transmitter is anticipating incoming MR returning active, which it will do one frame time after it is deactivated, unless an abort is signaled from the receiver. After the last
End-of-Transmission (EOM)
The transmitter sends an EOM in response to the EOM request bit being set in PPCR1. Once the EOM bit is set, the EOM is transmitted as soon as the Monitor Transmit Data Register becomes empty. This is normally done when the last byte of a message has been transmitted. The DSC/IDC circuit transmits an EOM simply by not reactivating MX after deactivating it in response to MR going inactive. The EOM request bit in PPCR1 is automatically cleared when the EOM has been transmitted, indicating that the monitor transmitter is available for a new message.
Abort
An abort is a signal from the receiver to the transmitter indicating that data has been missed. The receiver sends an abort by holding MR inactive for two or more frames in response to MX going active. An interrupt is generated when an abort is received.
Flow Control
The transmitter is held off until the Monitor Receive Data Register is read, since MR is held active until the receive byte is read. The transmitter will not start the next transmission cycle until MR goes inactive.
AM79C30A/32A Data Sheet
55
MX Transmitter MX First Byte MR Receiver MR ACK n * 125 s 125 s a. General Case ACK ACK New Byte Last Byte
EOM
MX Transmitter MX New Byte MR Receiver MR
EOM
Abort Request b. Abort Request from the Receiver
MX Transmitter MX First Byte MR Receiver MR First Byte ACK Second Byte ACK Third Byte Second Byte Third Byte EOM
c. Maximum Speed Case Figure 12. Monitor Handshake Timing
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56
AM79C30A/32A Data Sheet
IOM-2 Activation/Deactivation The IOM-2 Interface includes an activation/deactivation capability (see Figure 13). Activation and deactivation can be initiated from either upstream or downstream components on the bus. When deactivated, the upstream device holds all the clock outputs Low, and the downstream devices force their open drain data outputs to a High-Z state (seen as a High on the system bus due to the external pullup resistor). The activation/deactivation procedure is a combination of software handshakes via the C/I channel, and hardware indications via the clock and data lines. The IOM-2 specification describes both the hardware and software protocols in detail; the hardware operation supported by the AM79C30A IOM-2 implementation is outlined in Figure 13.
DSC/IDC Circuit as Upstream Device (Clock Master)
Deactivation
D e a c t iva t io n o f t h e IO M -2 I n t e r fa c e f ro m th e AM79C30A operating as an upstream device is initiated and controlled by the microprocessor. A series of software handshakes via the C/I channel must be performed before the hardware deactivation can take place. The upstream device must issue a deactivation request command on the C/I channel and wait for a deactivation indication from all downstream units. Once this is received, a deactivation confirmation command must be sent on the C/I channel by the upstream device. The upstream device will then stop all clocks and hold them Low. On the AM79C30A, the IOM-2 clocks (SCLK,SFS, and BCL/CH2STRB) are stopped and forced Low when the microprocessor clears the activation/deactivation bit in the Peripheral Port Control
SBIN goes Low Timing Request Interrupt generated
Idle (clks off)
clk pend (clks off)
Software clears Activation bit
Software sets Activation bit
Software sets Activation bit
ACTIVE (clks on)
a. AM79C30A as Upstream Device Idle (clks off) (SBIN = Z)
Software sets Activation bit SBIN output forced Low (SBIN = 0) (clks off)
SBIN output forced to Z
Clock received from upstream; Timing Request interrupt generated (SBIN = 0) (clks on) Software sets Activation bit ACTIVE (clks on) (SBIN = data)
Timeout (clks off)
Clocks stopped by upstream device
a. AM79C30A as Downstream Device
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Notes: This diagram shows only the portions of the IOM-2 activation/deactivation procedures that are affected by the AM79C30A hardware. The C/I-channel software handshakes are not shown.
Figure 13.
IOM-2 Activation/Deactivation
AM79C30A/32A Data Sheet
57
Register Number 1 (PPCR1). When this bit is cleared, the data output pin (SBOUT) is also forced to High-Z (seen as a High on the system bus due to the external pullup resistor), and the AM79C30A begins monitoring the data input pin (SBIN) for the presence of a timing request from any downstream units.
Low and allow the processor to complete the activation procedure by sending the proper commands over the C/I channel. When the activation is originated from the upstream device, the AM79C30A will generate an IOM-2 timing request interrupt (bit 6 in PPSR) when the IOM-2clocks become active as indicated by the SCLK input pin going High. The AM79C30A will begin normal IOM-2 transmission/reception as soon as SCLK appears; no intervention from the microprocessor is required. However, the processor must respond to the interrupt and perform the normal C/I channel software handshakes before activation will be complete.
Activation
Activation can be initiated locally by the processor or remotely by one of the downstream units. To activate locally, the processor sets the activation/deactivation bit in PPCR1 (starting the clocks), and then proceeds through the software activation protocol on the C/Ichannel. For remote activation, the upstream device receives a request from the downstream device via the data input pin. When the data input pin (SBIN) goes Low, AM79C30A will generate an IOM-2 timing-request interrupt, bit 6 in the Peripheral Port Status Register (PPSR). The processor must respond to this interrupt, and restart the IOM-2 clocks by setting the activation/deactivation bit in PPCR1. Once the clocks are running, the downstream device can request full activation via the C/I channel using the IOM-2 software protocol. DSC/IDC Circuit as a Downstream Device (Clock Slave)
TIC Bus Operation
C/I0 Channel Arbitration Software control for the IOM-2 Bus Accessed (BAC) bit will be added at bit 7 of CITDR0, which is currently reserved. It will be referred to as the BAR, "Bus Access Request" bit. This bit will be used to gain access to the C/I0 channel when TIC bus supp or t is enabled (PPCR3.3=1). The BAR bit should be set whenever the DSC has C/I0 data available to transmit. When CITDR0.7=1, the TIC bus will arbitrate access to the C/I0 channel with other devices on the IOM-2 interface using the TIC address programmed into PPCR3.2-0. The TIC bus control logic will check to see if the BAC bit on the line is 0 or 1 to determine if another downstream device currently owns the bus. If zero, the DSC will wait. Once a one is detected in BAC, the logic will place the DSC's TIC bus address on the open drain output. It will then sample this output with the IOM-2 received data strobe timing to check for conflict with other downstream devices. If the received TIC address and the contents of PPCR3.2-0 match, the logic will set the BAC output to "0" indicating to other downstream devices that the DSC has taken control of the D and C/I0 channels. After it sets its BAC output to 0, the logic will compare the TIC address on the line with PPCR3.2-0 in one more frame to ensure ownership of the bus. If a miscompare occurs, the DSC will set its BAC output to 1 and return to the beginning of arbitration. Once access is gained, the D and C/I0 channels are the possession of the DSC. This allows the DSC to complete C/I0 communication with the Layer 1 device without interruption from other downstream devices. (Since the TIC bus is used for arbitration of both D and C/I0 channel communication, gaining access for one implicitly gives you access to the other). After the DSC completes C/I0 communication, software should set CITDR0.7=0 to allow other downstream devices access to the D and C/I0 channels. The logic will set the BAC bit output of the DSC back to 1, as long as the
Deactivation
Deactivation is normally initiated by the upstream device as described above. When the deactivation request is received by the downstream device over the C/I channel, the processor must respond by sending the deactivation indication over the C/I channel. The upstream device will then send the deactivation confirmation command over the C/I channel and stop the IOM-2 clocks. The AM79C30A will detect that the clock has stopped (defined as no clock pulse received for 650 ns) and force itself to the deactivated state. In the deactivated state, SBIN, and SBOUT are both forced to a High-Z state, and the SCLK input is monitored for any rising edge that would indicate an activation request from the upstream device.
Activation
Once again, activation can originate from either the upstream or the downstream device. To activate the interface from the downstream device, the processor sets the activation/deactivation bit in the PPCR1 register. This will force the AM79C30A to pull its data output pin (SBIN in this case, since the I/O pin definition is reversed when talking to the upstream device) Low, causing the upstream device to start the IOM-2 clocks. Once the clocks are running, as indicated by SCLK input going High, the AM79C30A will generate an IOM-2 timing request interrupt (bit 6 in PPSR). The processor must respond to the interrupt by loading the proper C/I command response into C/ITRDO, then clearing the activation/deactivation bit in PPCR1. This will release the data output pin (SBIN) from being held
58
AM79C30A/32A Data Sheet
DSC has no D-channel communications also in progress. A priority scheme is included to prevent the DSC from dominating the bus. A new bus access will not be allowed until the device detects BAC bit set to 1 in two successive frames. Care must be taken in use of the Bus Access Request bit (CITDR0.7). As stated above, once access is gained through use of this bit, the DSC will control the D and C/I0 channels as long as it remains set. Software must remember to clear this bit to allow other devices access. D-Channel Arbitration When the TIC bus feature is enabled (PPCR3.3=1), the DLC will automatically request TIC bus access without software intervention. The access procedure is much the same as the C/I0 channel above. The TIC bus control logic will check to see if the BAC bit on the line is 0 or 1 to determine if another downstream device currently owns the bus. If zero, the DSC will wait. Once a one is detected in BAC, the logic will place the DSC's TIC bus address on the open drain output. It will then sample this output at the IOM-2 received data strobe point to check for conflict with other downstream devices. If the received TIC address and
the contents of PPCR3.2-0 match, the logic will set the BAC output to 0 indicating to other downstream devices that the DSC has taken control of the D and C/I0 channels. After is sets its BAC output to 0, the logic will compare the TIC address on the line with PPCR3.2-0 in one more frame to ensure ownership of the bus. If a miscompare occurs, the DSC will set its BAC output to 1 and return to the beginning of arbitration. Once access is gained, the D and C/I0 channels are the possession of the DSC. This allows the DSC to complete D-channel communications with the Layer 1 device without interruption from other downstream devices. After the DSC completes D-channel communication, logic will set the DSC's BAC bit output back to 1, as long as the BAC request bit (CITDR0.7) is not set. This allows other downstream devices access to the D and C/I0 channels. If CITDR0.7=1, the device assumes C/I0 communication is still in progress and the BAC output remains 0 until software clears CITDR0.7. A priority scheme is included to prevent the DSC from dominating the bus. A new bus access will not be allowed until the device detects BAC bit set to 1 in two successive frames.
AM79C30A/32A Data Sheet
59
Peripheral Port Registers
The PP contains the following registers:
Registers Peripheral Port Control Register Peripheral Port Status Register Peripheral Port Interrupt Enable Register Monitor Transmit Data Register Monitor Receive Data Register C/I Transmit Data Register C/I Receive Data Register # of Registers 3 1 1 1 1 2 2 Mnemonic PPCR1, PPCR2, PPCR 3 PPSR PPIER MTDR MRDR CITDR0, CITDR1 CIRDR0, CIRDR1
Peripheral Port Control Register 1 (PPCR1) Default = 01 Hex Address = Indirect C0 Hex, Read/Write
7 MONTR ABORT RQST 6 MONTR ENABL 5 MONTR CHANL SELECT 4 MONTR EOM RQST 3 IC CHANL SELECT 2 IOM 2 ACTV/ DEACT 1 PORT MODE SELECT BIT 1 0 PORT MODE SELECT BIT0
Bit 7 6
Function Monitor Channel Abort Request--This bit is automatically cleared during RESET or manually by software as follows: to send an ABORT message, software should set this bit, wait at least two frames, then clear the bit. Monitor Channel Enable--This bit only affects IOM-2 operation. When set, the selected monitor channel is enabled. When cleared, both monitor channels are disabled. Whenever the monitor channel is disabled, the Monitor Transmit and Receive Data Register (MTDR, MRDR) are updated to their default states: MTDR = FFH, MRDR = 00H. Monitor Channel Select--This bit only affects IOM-2 operation. When set, Monitor channel 1 is used (second subframe). When cleared, Monitor channel 0 is used (first subframe). Monitor End-of-Message Request--When set, this bit forces the Monitor channel transmitter to send an EOM once all data written into the Monitor Transmit Data Register has been transmitted. This tells the receiving device that the message is complete. The bit is cleared by hardware when the EOM is sent by reset or by software. IC Channel Select--This bit only affects IOM-2 operation. When set, the IC2 time slot is used (sixth octet after the frame sync). When cleared, the IC1 time slot is used (fifth octet after the frame sync). The unused channel is always placed in a high-impedance state. IOM-2 Activation/Deactivation Bit--This bit only affects IOM-2 operation. Note that this bit controls only the starting and stopping of SCLK, BCL/CH2STRB, SFS, and the state of the SBIN/SBOUT pins; this alone does not constitute activation or deactivation of the IOM-2 bus. The activation/deactivation procedure involves the exchange of a series of commands and indications over the C/I channel. This procedure, including a state diagram, is detailed in the IOM-2 specification. IOM-2 Master mode--This bit is set by software. When deactivated, the master will turn on SCLK, BCL/CH2STRB, and SFS clocks via software by setting this bit when the SBIN pin is pulled Low, indicating that a downstream device wishes to communicate over the interface. The IOM-2 activation/deactivation bit is cleared by software or reset. When cleared, the clocks are stopped, and SBIN is monitored for the reactivation request from the slave (SBIN held Low). [Reset defaults the Peripheral Port to SBP operation.] IOM-2 Slave mode--This bit is set by software to initiate an activation request to the master. When set, the SBIN pin is driven Low, and held Low until the activation/deactivation bit is cleared by software. In response to SBIN going Low the master will start SCLK, which generates a timing request interrupt in the DSC circuit. The activation/deactivation bit is cleared by software in response to this interrupt.
5 4
3
2
60
AM79C30A/32A Data Sheet
Peripheral Port Control Register 1 (PPCR1) -- (continued)
Bit 1-0 Function Port Mode Select Field--These two bits select the configuration of the Peripheral Port as follows. Bit 1 0 0 1 1 0 0 1 0 1 Function Port Disabled SBP mode enabled IOM-2 Slave mode enabled IOM-2 Master mode enabled
When the port is disabled, SBOUT, SBIN, and all port-related clocks are placed in a high-impedance state. When the DSC circuit is reset, this bit field is set to 01, and the port is not enabled until a MUX MCR register is written to. If this bit is cleared prior to such a path being programmed, the port will remain disabled until the bit is set via a software write operation.
Peripheral Port Status Register (PPSR) Default = Bit 1 = 1, Bits 6-2 and 0 = 0, Bit 7 is Indeterminate Address = Indirect C1 Hex, Read
7 6 IOM-2 TIME RQST 5 CHNG IN C/I 1 DATA 4 CHNG IN C/I 0 DATA 3 MONTR ABORT RECVD 2 MONTR EOM RECVD 1 MONTR XMIT BUFFR AVAIL 0 MONTR RECV DATA AVAIL
RSRVD
The Peripheral Port Status Register presents various status conditions to the user, and is only used in the IOM-2 mode. Each of these conditions can generate an interrupt to the user. The interrupts are enabled via the Peripheral Port Interrupt Enable Register. The state of the respective interrupt enable bits does not affect the setting of bits in this register. Bits 6, 3, and 2 are cleared when this register is read. Bit 1 is cleared when the Data Register is written, and bit 0 is cleared when the Data Register is read. In addition, bits 3, 2, 1, and 0 are cleared when the Monitor channel is disabled (via bit 6 of the PPCR1 Register). Because bit 7 is reserved, the default value of this register is either 02H or 82H.
Bit 6 Function IOM-2 Timing Request--When the DSC circuit is the upstream device (master mode), this bit is set by hardware to indicate that a downstream device has requested the starting of the IOM-2 clocks. The clocks are started by software. This bit does not indicate the receipt of an activation request on the C/I channel. When the DSC circuit is the downstream component (slave mode), this bit is set in response to SCLK starting (going High) when the bus is deactivated.
5 4 3
2 1 0
Notes: 1. The DSC circuit will not exit Power-Down mode in response to either a timing request or the clocks being started if this interrupt is masked. It is essential that an interrupt be generated when the DSC circuit leaves Power-Down mode. Otherwise, power consumption could increase significantly without the processor's knowledge. Change in C/I 1 Channel Status--This bit is set by hardware to indicate that the contents on the receive side of C/I channel 1 have changed since the C/I Receive Data Register was last read. Change in C/I 0 Channel Status--This bit is set by hardware to indicate that the contents on the receive side of C/I channel 0have changed since the C/I Receive Data Register was last read. Monitor Channel Abort Request Received--This bit is set by hardware to indicate that an abort request has been received on the monitor channel. This indicates that the receiver on the other end of the Monitor channel has failed to receive the transmitted data correctly and requests that the current transmission be discontinued and the data transmission repeated via software. Monitor Channel End-of-Message Indication Received--This bit is set by hardware to indicate that an abort request has been received on the monitor channel. This indicates that the message currently being received has concluded. Monitor Channel Transmit Buffer Available--This bit is set by hardware to indicate that a new byte of data can be loaded into the Monitor Transmit Data Register. Monitor Channel Receive Data Available--This bit is set by hardware to indicate that a byte of data has been received on the monitor channel and is available in the Monitor Receive Data Register.
AM79C30A/32A Data Sheet
61
Peripheral Port Interrupt Enable Register (PPIER) = 1 Default = Write = 00 Hex, Read = Bit 7 = 1, Bits 6-0 = 0 Address = Indirect C2 Hex, Read/Write
7 6 ENABL IOM-2 TIME RQST 5 ENABL CHNG IN C/I1 DATA 4 ENABL CHNG IN C/I0 DATA 3 ENABL MONTR ABORT RECVD 2 ENABL MONTR EOM RECVD 1 ENABL MONTR XMIT BUFFR AVAIL 0 ENABL MONTR RECV DATA AVAIL
PP/MF INT EN
The Peripheral Port Interrupt Enable Register provides an individual interrupt-enable bit corresponding with eachof the status conditions in the Peripheral Port Status Register. When set, the interrupt is enabled. Clearing the bit disables the interrupt. These bits are set and cleared by software.
Bit 7 Function PP/MF Interrupt Enable--When set, this bit enables the Peripheral Port and Multiframing interrupts. When cleared, the PP and MF interrupts are disabled.
Notes: To ensure proper interrupt reporting, software must disable PP/MF interrupts when the interrupt routine is entered and enable them when exiting.
Monitor Transmit Data Register (MTDR) Default = FF Hex Address = Indirect C3 Hex, Write
7 DATA BIT 7 (MSB) 6 DATA BIT 6 5 DATA BIT 5 4 DATA BIT 4 3 DATA BIT 3 2 DATA BIT 2 1 DATA BIT 1 0 DATA BIT 0 (LSB)
The Monitor Transmit Data Register is the user-visible portion of the Monitor channel Transmitter Data buffer. Data is written into this register by the user in response to a monitor transmit buffer available interrupt. It is then transmitted to the receiver on the other side of the IOM-2 bus. The MTDR is emptied when the PP is reset. Monitor Receive Data Register (MRDR) Default = 00 Hex Address = Indirect C3 Hex, Read
7 DATA BIT 7 (MSB) 6 DATA BIT 6 5 DATA BIT 5 4 DATA BIT 4 3 DATA BIT 3 2 DATA BIT 2 1 DATA BIT 1 0 DATA BIT 0 (LSB)
The Monitor Receive Data Register is the user-visible portion of the Monitor channel Receiver Data buffer. Data is written into this register by the hardware as it is received over the monitor channel. A monitor data available interrupt is generated when the register is loaded. The register is overwritten by hardware only after the register has been read. The default on reset is 00 hex.
62
AM79C30A/32A Data Sheet
C/I Transmit Data Register 0 (C/ITDR0) Default = 0F Hex Address = Indirect C4 Hex, Write
7 Bus Access Request 6 5 4 3 C/I0 DATA BIT 3 (MSB) 2 C/I0 DATA BIT 2 1 C/I0 DATA BIT 1 0 C/I0 DATA BIT 0 (LSB)
RSRVD
RSRVD
RSRVD
The C/I Transmit Data Register 0 is the user-visible portion of the C/I channel 0 transmitter. Data can be written into this register by the user at any time and is transmitted continuously during each subsequent frame until changed.The register is set to its default value, 0F hex (C/I channel idle), by reset or disabling of the Peripheral Port. Bus access request bit-When set, the DSC will attempt to gain access to the C/I0 channel if TIC bus is enabled. C/I Receive Data Register 0 (C/IRDR0) Default = XF Hex Address = Indirect C4 Hex, Read
7 6 5 4 3 C/I0 DATA BIT 3 (MSB) 2 C/I0 DATA BIT 2 1 C/I0 DATA BIT 1 0 C/I0 DATA BIT0 (LSB)
RSRVD
RSRVD
RSRVD
RSRVD
The C/I Receive Data Register 0 contains data valid for two frames from C/I Receive channel 0. The register is set to its default value of XF hex by a reset or the disabling of the Peripheral Port. C/I Transmit Data Register 1 (C/ITDR1) Default = 3F Hex Address = Indirect C5 Hex, Write
7 6 5 C/I1 DATA BIT 5 (MSB) 4 C/I1 DATA BIT 4 3 C/I1 DATA BIT 3 2 C/I1 DATA BIT 2 1 C/I1 DATA BIT 1 0 C/I1 DATA BIT 0 (LSB)
RSRVD
RSRVD
The C/I Transmit Data Register 1 is the user-visible portion of the C/I channel 1 transmitter. Data can be written into this register by the user at any time. It is transmitted continuously during each subsequent frame until changed. The register is set to its default value, 3F hex (C/I channel idle), by reset or disabling of the Peripheral Port. C/I Receive Data Register 1 (C/IRDR1) Default = Bits 7 and 6 are Indeterminate, Bits 5-0 = 1 Address = Indirect C5 Hex, Read
7 6 5 C/I1 DATA BIT 5 (MSB) 4 C/I DATA BIT 4 3 C/I1 DATA BIT 3 2 C/I1 DATA BIT 2 1 C/I1 DATA BIT 1 0 C/I1 DATA BIT 0 (LSB)
RSRVD
RSRVD
The C/I Receive Data Register 1 contains the data (valid for two frames) from C/I Receive channel 1. The register is set to its default value by a reset or the disabling of the Peripheral Port.
AM79C30A/32A Data Sheet
63
Peripheral Port Control Register 2 (PPCR2) Default = Bits 7, 6, and 0 = 0, Bit 5 = 1, Bits 4-1 are Indeterminate* Address = Indirect C8 Hex, Read/Write
7 REV CODE BIT 2 (MSB) 6 REV CODE BIT 1 5 REV CODE BIT 0 (LSB) 4 3 2 1 0 SCLK INVRT ENABL
RSRVD
RSRVD
RSRVD
RSRVD
The Peripheral Port Control Register 2 controls the inversion of the SCLK output in SBP mode. This provides flexibility in the connection of peripheral devices to the DSC circuit. The hardware revision code is also contained in this register, which allows software to identify the revision of the hardware.
Note: * The default value is revision-level dependent. Revision J will report a hardware revision code of 110.
Bit 7-5 0 Function Hardware Revision Code--This read-only field reports the hardware revision level. Revision J of the DSC circuit will report a hardware revision code of 110. The hardware revision codes for E and H are 100, 010, respectively. SCLK Inversion Enable--When set, the SCLK output is inverted in SBP mode. When cleared, the SCLK output is identical to the Revision D DSC circuit. This bit should not be changed while SCLK is enabled.
Peripheral Port Control Register 3 (PPCR3) Default = Bits 7-5 are Indeterminate, Bit 4=1, Bit 3=0, Bits 2-0= 1 Address = Indirect C9 Hex, Read/Write
Bit 7-5 4 Function RESERVED SLAVE Mode Bus Reversal--PPCR3.4 controls the bus reversal function of the DSC's IOM-2 SLAVE mode. By default (PPCR3.4=1) the Slave bus reverses to ensure backwards compatibility with previous revisions. When PPCR3.4=0 the IOM-2 bus will not reverse in SLAVE mode. This assures slave compatibility of the control function and allows use with devices such as the ISAC-S. TIC Bus Enable--PPCR3.3 controls enabling and disabling of TIC bus operation. When PPCR3.3=0 which is the default condition, the IOM-2 bus will not support the TIC bus feature to ensure backwards compatibility with previous IOM-2 capable revisions of the 79C30A. The TIC bus control logic features are only enabled if PPCR3.3=1. Features enabled when PPCR3.3=1 S/G bit When the DSC is in IOM-2 MASTER mode the CTS output of the LIU is used to drive the transmitted S/G bit. This signal indicates D-channel Clear To Send status and is set when the LIU collision detection logic fulfills the programmed priority level requirements. When in IOM-2 SLAVE mode the received S/G bit is used as the Clear To Send input into the DLC block. TIC Address Bus and Bus Accessed 2-0 Refer to TIC bus operation section. TIC Bus Address--Device address to be used on TIC bus. Default is 111.
3
64
AM79C30A/32A Data Sheet
APPLICATIONS
ISDN Feature Phone This basic feature phone is the ISDN equivalent to the common analog phone. The keypad can be a simple four-by-four single-pole switch-matrix or a larger-matrix to provide full-key system features. The display option illustrated in Figure 14 can be included in any of theapplications shown in this section. ISDN Feature Phone with Parallel and Serial Data Ports Plus Other Peripherals Access to the CCITT R reference interface is provided via both the serial and parallel ports in Figure 15. This application may easily have voice capability added by using a DSC circuit in place of the IDC circuit. Figure 16 illustrates applications with increased B-channel data processing requirements.
AM79C30A DSC Circuit Telephone Speaker PP Audio Processor B-Channel MUX Surge Protection S/T Interface
LIU
Hook Switch OSC MCLK
MPI
D-Channel DLC
Interrupt RAM ROM Power Reversal Interrupt Microcontroller Power Controller
5V
Keypad
LCD Display
09893H-10
Figure 14.
ISDN Telephone
AM79C30A/32A Data Sheet
65
Speaker
PSB2110 ISGN Terminal Adaptor Circuit Terminal Interface V.110 Processor Serial Port
Tone Am79C32A DSC Circuit B-Channel MUX Surge Protection
Terminal Port UART HDLC
PP
LIU
S/T Interface
OSC
MPI
D-Channel DLC
FIFO
FIFO
Microprocessor Interface
Interrupts 3
MCLK
Power Reversal Interrupt
Power Controller
Microcontroller
RAM
ROM
5V
09893H-11
Figure 15.
Terminal Adapter (V.110/V.120) With Voice Upgrade Capability
66
AM79C30A/32A Data Sheet
Analog Telephone Interface Am85C30 or PSB82525 AM79C30A DSC Circuit Audio Processor B-Channel MUX Surge Protection
Data Link Controller
Data Link Controller PP
LIU
S/T
Microprocessor Interface D-Channel DLC
MPI DMA Controller
80188 DMA Timers Interrupts CPU Chip Selects Am85C30/PSB82525 DSC Circuit Memory Clock PC Bus PC Bus Interface Dual-Port Dual-Port RAM RAM Controller Interface ROM Optional Program DRAM Memory Controller
Figure 16.
PC Add-On Board (1 or 2 Data Channels)
09893H-12
AM79C30A/32A Data Sheet
67
ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings
Storage temperature -65C to +150C Ambient temperature with power applied . . . . . . . . . . . . . -55C to +125C Supply voltage to ground, potential continuous . . . . . . . . . . . . . . . 0 V to +7.0 V Lead temperature (soldering, 10 sec) . . . . . . . . 300C Maximum power dissipation . . . . . . . . . . . . . . . 1.5 W Voltage from any pin to VSS . . . . . . . . . . . . .VSS - 0.5 V to VCC + 0.5 V DC input/output current (except LS1, LS2) . . . . . . . . . . . . . . . . . . . . . . . 10 mA
DC output current, LS1, LS2 only . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Operating Ranges
Commercial (C) devices Operating VCC range with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . .4.75 V to 5.25 V Ambient temperature (TA) . . . . . . . . . . . 0C to +70C
Operating Ranges define those limits between which the functionality of the device is guaranteed.
DC Characteristics over Commercial Operating Ranges (unless otherwise specified)
Parameter Symbol Parameter Descriptions VIH VIH2 VIL VOL VOH IOL IIL Input High Level, except XTAL2 Input High Level XTAL2 Input Low Level Output Low Level, except SBOUT Output Low Level, SBOUT only Output High Level Output Leakage Current Input Leakage Current Digital Inputs LIN1/LIN2 XTAL2 CI CO Input Capacitance Digital Input Output Capacitance Digital Input/Output Temp = 255C Freq = 1 MHz Temp = 255C Freq = 1 MHz 10 (TYP) pF IOL = 2 A IOL = 7 A IOH = -400 A = -10 A 0 < VOUT < VCC Output in High-Z State 0 < VIN < VCC 10 200 5.5 (TYP) 10 (TYP) A A A pF 2.4 0.90 V CC 10 A Test Conditions Preliminary Min 2.0 0.80 V CC VSS - 0.25 Max VCC + .25 VCC + .25 0.80 0.40 0.40 V Unit V V V V
68
AM79C30A/32A Data Sheet
Table 51.
Revision E Power Specifications for CCITT-Restricted Mode Phone Operation
Test Conditions Preliminary Typ 4 Max 5 Unit
Parameter Parameter Symbol Descriptions ICC0
VCC = 5.25 V; VIH = VCC; VIL = VSS; mode = Power-Down; VCC Supply Current Clocks & Oscillator Stopped; LIU Receiver Enabled; S Interface (Power-Down mode) Silent (INFO 0) VCC Supply Current (Idle mode) VCC = 5.25 V; VIH = VCC; VIL = VSS; mode = Idle, Data Only; fMCLK = 3.84 kHz; LIU Receiver Enabled; S Interface Silent (INFO 0)
mW
ICC1
20
25
mW
ICC2
VCC = 5.25 V; VIH = VCC; VIL = VSS; mode = Active, Data Only; VCC Supply Current fMCLK = 3.072 MHz; LIU Receiver and Transmitter Enabled; S (Active; Call Set-Up) Interface Activated with Data on D-Channel Only; S-interface Load = 50 ohms VCC = 5.25 V; VIH = VCC; VIL = VSS; mode = Active Voice & Data; fMCLK = 384 MHz; LIU Receiver and Transmitter Enabled; VCC Supply Current S Interface Activated with Data on D-channel and one (Active; Voice mode) B-channel; S-interface Load = 50 ohms, AINA = -15 dBm0, 1-kHz Sine Wave; EAR1/EAR2 = -15 dBm0, 1-kHz Tone Driving 600 ohms VCC Supply Current (Active; Ringing, No Load*) VCC = 5.25 V; VIH =VCC; VIL = VSS; mode = Active, Data Only; fMCLK = 384 kHz; LIU Receiver and Transmitter Enabled, S Interface Activated with Data on D-channel Only; S-Interface Load = 50 ohms; Secondary Tone Ringer Enabled at 0 dB, 400 Hz, No Load
80
105
mW
ICC3
155
190
mW
ICC4
125
150
mW
Note: All power measurements assume PP disabled or in IOM-2 Deactivated mode.
OUT *Power consumption with the output loaded will be I CC 4 + ---------------------------------- ( V CC )
(V
,peak )
R LOAD
AC CHARACTERISTICS
VCC = 5 V 5%; VSS = 0 V; TA = 0C to 70C; MCLK = 3.072 MHz
Table 52.
Parameter Parameter Descriptions Symbol ZIN VIOS LLS LEAR Analog Input Impedence AINA or AINB to AREF Allowable Offset Voltage at AINA or AINB Allowable Load LS1 to LS2 Allowable Load EAR1 to EAR2
MAP Analog Characteristics (AM79C30A only)
Test Conditions -1.25 V < V IN < +1.25 V fIN < 4 kHz with respect to AREF pin Preliminary Min 200 -5 RLOAD > 40 ohms and CLOAD < 100 pF RLOAD > 130 ohms and CLOAD < 100 pF RLOAD > 1 Kohm and CLOAD < 100 pF 2.1 2.25 2.4 V +5 Typ Max Unit Kohm mV
LAREF VAREF
Allowable Load AREF to VSS or VCC Analog Reference Voltage
AM79C30A/32A Data Sheet
69
MAP Transmission Characteristics (AM79C30A only)
The codec is designed to meet CCIIT Recommendation G.714 requirements for signal to distortion, gain tracking, frequency response, and idle channel noise specification as defined in Table 53. Verification of conformance to G.714 is by device characterization. Production testing of individual par ts includes those parameters shown in Table 54. Half-channel parameters are specified from AINA or AINB input pins to a B channel for the transmit path, Table 53.
and from a B channel to EAR1/EAR2 or LS1/LS2 pins measured differentially for the receive path. These parameters are applicable for both A- or -law conversion. (A-law assumes psophometric filtering, and -law assumes c-message weighting). All parameters are specified with the GR, X, R, GX and GER filters disabled; STG filter is enabled but programmed for infinite attenuation. All values are for V cc=5V +5%, TA = 0-70C, and programmable filters/gains disabled (0 dB, flat) unless otherwise indicated.
MAP Transmission Characteristics (AM79C30A only)
Test Conditions Preliminary Min 24.0 -0.25 -0.25 -0.25 -0.25 0.0 9.0 -0.25 -0.25 -0.25 -0.25 0.0 9.0 Typ Max Unit dB dB dB dB dB dB dB dB dB dB dB dB dB s s s s s s s s dB dB dB dB dB dB +0.3 +0.6 +1.6 +0.3 +0.6 +1.6 -82 -79 -76 -73 -70 -90 -80 -78 -75 -72 -69 -66 -85 -75 dB dB dB dB dB dB dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0
Parameter Symbol Parameter Descriptions
TXF
*50 Hz-60 Hz < 300 Hz 0.3 kHz-3.0 kHz Transmit Frequency Response (Attenuation vs. Frequency Relative to -10 dBm0 at 1020 Hz)--see 3.0 kHz-3.4 kHz 3.4 kHz-3.6 kHz Figure 17 3.6 kHz-3.9 kHz 3.9 kHz-4.0 kHz <300 Hz 0.3 kHz-3.0 kHz Receive Frequency Response (Attentuation vs. 3.0 kHz-3.4 kHz Frequency Relative to -10 dBm0 at 1020 Hz)--see 3.4 kHz-3.6 kHz Figure 21 3.6 kHz-3.9 kHz 3.9 kHz-4.0 kHz 500 Hz-600 Hz Transmit Group Delay Variation vs. Frequency at 600 Hz-1000 Hz -10 dBm0 Relative to Minimum Delay Frequency-- 1.0 kHz-2.6 kHz see Figure 18 2.6 kHz-2.8 kHz 500 Hz-600 Hz Receive Group Delay Variation vs. Frequency at 600 Hz-1000 Hz -10 dBm0 Relative to Minimum Delay Frequency-- 1.0 kHz-2.6 kHz see Figure 22 2.6 kHz-2.8 kHz Transmit Signal/Total Distortion vs. Level; CCITT Method 2, 1020 Hz (Transmit Gain = 0dB)--See Figure 20 Receive Signal/Total Distortion vs. Level; CCITT Method 2, 1020 Hz (Transmit Gain = 0dB)--See Figure 24 0 to -30 dBm0 -40 dBm0 -45 dBm0 0 to -30 dBm0 -40 dBm0 -45 dBm0
+0.25 +0.9
RXF
+0.25 +0.9
TXD
750 380 130 750 750 380 130 750 35.0 29.0 24.0 35.0 29.0 24.0 -0.3 -0.6 -1.6 -0.3 -0.6 -1.6
RXD
TXSTD
RXSTD
TXGT
+3 to -40 dBm0 Transmit Gain Tracking vs. Level; CCITT Method 2, -40 to -50 dBm0 1020 Hz (Transmit Gain = 0 dB)--See Figure 19 -50 to -55 dBm0 +3 to -40 dBm0 Receive Gain Tracking vs. Level; CCITT Method 2, -40 to -50 dBm0 1020 Hz (Receive Gain = 0 dB)--See Figure 23 -50 to -55 dBm0 Transmit Idle channel Noize AINA or AINB Connected to AREF GX = GX = GX = GX = GX = 0 dB, GA = 0 dB 6 dB, GA = 0 dB 6 dB, GA = 6 dB 6 dB, GA = 12 dB 6 dB, GA = 18 dB
RXGT
TXICN
RXICN
Receive Idle channel Noise
GR = 0 dB, GER = 0 dB GR = -12 dB, GER = 0 dB
Note: *Measured with the high pass filter and auto-zero enabled in MMR2.
70
AM79C30A/32A Data Sheet
Table 54.
Codec Performance Specifications (AM79C30A only)
Test Conditions 0 dBm0; 1020 Hz; VCC = 5 V 5%, TA = 0C-70C; over all GA 0 dBm0; 1020 Hz; VCC = 5 V 5%; TA = 0C-70C; Rload = 540 ohms 0 dBm0; 1020 Hz; VCC = 5 V 5%; TA = 0C-70C; Rload = 40 ohms -10 dBm0 -45 dBm0 Preliminary Min -0.50 -0.50 -0.80 35 24 35 24 -0.60 -0.60 +0.60 +0.60 -66 -75 Max +0.50 +0.50 +0.80 Unit dB dB dB dB dB dB dB dB dB
Parameter Parameter Descriptions Symbol TXG RXGE RXGL TXSTD RXSTD TXGT RXGT TXICN RXICN Transmit absolute gain Receive absolute gain at EAR1/EAR2 (nominal) Receive absolute gain Transmit signal/total distortion; CCITT method 2, 1020 Hz (Tx gain = 0)
Receive signal/total distortion; CITT method 2, -10 dBm0 1020 Hz (Rx gain = 0) -45 dBm0 Transmit gain tracking; CCITT method 2, 1020 -45 Hz (Tx gain = 0) Receive gain tracking; CCITT method 2, 1020 Hz (Rx gain = 0) -45
Transmit Idle channel Noise AINA connected to GX = 6 dB, GA = 18 dB AREF Receive Idle channel Noise GR = -12 dB, GER = 0 dB
Notes: The following test conditions apply to all MAP tests: 1. An external 1-Kohm 5% resistor and 2200-pF 10% capacitor are connected in series between the CAP1 and CAP2 pins for all transmit tests. 2. All tests are half-channel with the sidetone path enabled but programmed for infinite attentuation (STG = 9008 hex). 3. Transmit specs are guaranteed for both AINA and AINB inputs with the auto-zero and high-pass filters enabled in MMR2. 4. Transmit specs are tested and guaranteed with the input signal source referenced to AREF; see test circuit below. 5. Receive specs are guaranteed for both EAR1/EAR2 and LS1/LS2 outputs measured differentially. Some degradation in performance may occur if used single ended rather than differential.
Transmitter 0-dB Reference Point: Nominal input voltage at AINA or AINB will produce a 0-dBm, 1-kHz digital code at the transmit output with all transmit gains at 0 dB. A law = 625 mV rms law = 620 mV rms Receiver 0-dB Reference Point: Nominal input voltage between EAR1/EAR2 or LS1/LS2 resulting from a 0-dBm, 1-kHz digital code at the receive input with all receive gains at 0 dB. A law = 1.25 mV rms law = 1.2 mV rms
0.1 F AINA or AINB ~ 100K AREF Transmit Test Circuit with Input Source Referenced to AREF
AM79C30A/32A Data Sheet
71
34 dB
9 dB
0.9
Attenuation (dB)
0.25 0 -0.25 1020 3000 3400 3600 3900 300 50 60
Frequency (Hz) Figure 17. Attenuation/Frequency Distortion (Transmit)
09893H-13
750
Group Delay (s)
380
130
500
600
1000
2600 2800
09893H-14
Frequency (Hz) Figure 18. Group Delay Variation with Frequency (Transmit)
72
AM79C30A/32A Data Sheet
1.6
0.6 0.3 Gain Variation (dB)
-55 -50 -0.3 -0.6
-40
-10
+3
Input Level (dBm0)
-1.6
09893H-15
Figure 19.
Gain Tracking Error (Transmit) (CCITT Method 2 at 1020 Hz)
AM79C30A/32A Data Sheet
73
35
29
Signal-to-Total Distortion Ratio (dB)
24
0
-45
-40
-30
-10
0
09893H-16
Input Level (dBm0)
Figure 20.
Signal-to-Total Distortion Ratio (Transmit) (CCITT Method 2 at 1020 Hz)
9 dB
0.9
Attenuation (dB) 0.25 0 -0.25
300
1020 Frequency (Hz)
3000 3400 3600 3900
09893H-17
Figure 21.
Attenuation/Frequency Distortion (Receive)
74
AM79C30A/32A Data Sheet
750
Group Delay (s)
380
130
500
600
1000
2600 2800
09893H-16
Frequency (Hz) Figure 22. Group Delay Variation with Frequency (Receive)
1.6
0.6 0.3 Gain Variation (db)
-55 -0.3 -0.6
-50
-40
-10
+3
Input Level (dBm0)
-1.6
09893H-17
Figure 23.
Gain Tracking Error (Receive) (CCITT Method 2 at 1020 Hz)
AM79C30A/32A Data Sheet
75
35
29
Signal-to-Total Distortion Ratio (dB)
24
0 -45 -40 -30 -10 0
09893H-18
Input Level (dBm0) Figure 24. Signal-to-Total-Distortion Ratio (Receive) (CCITT Method 2 at 1020 Hz)
76
AM79C30A/32A Data Sheet
LIU Characteristics All of the parameters below are measured at the chip terminals and are consistent with 2:1 transformers.
Parameter Symbol Parameter Descriptions VLOUT VLIN ZOUT ZIN J PD PU PW Output mark amplitude measured between LOUT2 and LOUT1 (Note 1) Receivable input level measured between LIN2 and LIN1, with noise added as specified by CCITT I.430 section 8.6.2.1 (Note 2) Output impedence measured between LOUT2 and LOUT1 spacing condition Input impedence measured between LIN2 and LIN1 Timing extraction jitter on LOUT Total phase deviation (LOUT with respect to LIN) Pulse unbalanced measured between LOUT2 and LOUT1 (Note 1) Output pulse width measured between LOUT2 and LOUT1 (Note 1) Preliminary Min 2.210 530 20 20 -7 -7 -5 4.7 5.2 +7 +15 +5 5.7 Typ 2.326 Max 2.442 1800 Unit V mV Kohm Kohm % % % s
Notes: 1. See the equivalent test load circuit and pulse template in Figures 26 and 27. 2. The 530-mV receive input level is equivalent to 9.0 dB of attenuation from a nominal transmit level when measured at the LIN pins. Allowing 0.5-dB loss in the isolation transformer, and 1.0-dB loss in the input isolation resistors, this level will guarantee compliance to the CCITT receiver sensitivity spec of 7.5 dB when measured at the S reference point. 3. Typical receiver performance is 220 mV.
AM79C30A/32A Data Sheet
77
R2 LOUT2 + VLOUT LOUT1 - R1
2:1 + RL CL V (s-reference)
R3 LIN1
2:1
RL LIN2 R4
CL
V (s-reference)
09893H-19
Notes: 1. V(s-interface): Transmitter output at the S-interface reference point. 2. RL is the termination impedence at the S interface. 3. CL is the effective capacitance at the S interface. 4. R1 and R2 are the transmitter output series resistors; their value depends upon the characteristics of the pulse transformer (see Figure 28). 5. R3 and R 4 are required for multipoint operation to prevent loading of the line when power is removed from the terminal.
Figure 25.
System Interface to LIU
High Mark VLOUT
RL CL = 200 pF 200 ohms 50 ohms
50 ohms LOUT2 + VLOUT LOUT1 -
a 50%
b PW
c 50%
Low Mark
09893H-19
PU
b High Mark a
c Low Mark b
09893H-20
Figure 26.
Equivalent Test Load Conditions
Figure 27. Differential Output Signals Between LOUT2 and LOUT1 (Using the Test Circuit in Figure 24)
78
AM79C30A/32A Data Sheet
ILOUT R2 LOUT2 + VLOUT LOUT1 - R1
09893H-20
RSEC
RPRIM * N2
RCORD * N2 RL * N 2
Notes: 1. RSEC is the DC impedance of the transformer secondary (IC side of transformer). 2. RPRIM is the DC impedance of the transformer primary (line side of transformer). 3. RCORD is the DC impedance of the TE connecting cord; typically 4-6 ohms. 4. N is the transformer turns ratio (N = 2 for AM79C30A/32A). 5. RL is the S-interface line impedance (50 ohms). 6. ILOUT is the desired load current for the CCITT transmission templates (7.5 mA for 50-ohm line). 7. VLOUT is the nominal output voltage from the DSC/IDC line driver.
Figure 28.
Equivalent DC Circuit at LOUT Pins for Calculation of R1 and R2
Series Resistor Calculations
Equation 1
V LOU T I LOUT = -------------------------------------------------------------------------------------------------------------------------------------------------------------2 2 2 R 1 + R 2 + R SEC + ( R PRIM * N ) + ( R L * N ) + ( R CORD * N )
Equation 2
( V LOU T ) 2 2 2 R 1 + R 2 = --------------------- - R SEC - ( R PRI M * N ) - ( R L * N ) - ( R CORD * N ) ( I LOUT )
Equation 3 Let R1 = R 2 Equation 4
2 2 2 1 V LOUT R 1 + R 2 = -- ---------------- - R SEC - ( R PRIM * N ) - ( R L * N ) - ( R COR D * N ) 2 ILOUT
Notes:
N=2 RL = 50 ohms VLOUT = 2.326 V ILOUT = 7.5 mA Equation 5
1 R 1 = R 2 = 55.067 + -- { R SEC + ( 4 * R PRI M ) + ( 4 * R COR D ) } 2
Equation 5 should be used to determine the value of R1 and R 2 for the particular transformer used by each customer.
AM79C30A/32A Data Sheet
79
Microprocessor Read/Write Timing
Microprocessor Read Timing
Parameter Symbol tRLRH tRHRL tAVRL tAHRH tRHCH tRACC tRHDZ tRDCS Parameter Description RD Pulse Width Read Recovery Time (Notes 1, 2) Address Valid to RD Low Address Hold After RD High RD High to CS High (Note 7) Read Access Time (Note 3) RD High to Data Hi-Z RD Low to CS Low (Note 4) Min 200 200 20 10 0 80 50 30 Max Units ns ns ns ns ns ns ns ns
Microprocessor Write Timing
Parameter Symbol tWLWH tWHWL tAVWL tAHWH tWHCH tDSWH tDHWH tWRCS Parameter Description WR Pulse Width Write Recovery Time (Note 1) Address Valid to WR Low Address Hold After WR High (Note 8) WR High to CS High (Note 7) Data Setup to WR High Data Hold After WR High WR Low to CS Low (Note 4) Min 200 200 20 10 0 100 10 30 Max Units ns ns ns ns ns ns ns ns
Notes: 1. The read/write recovery time of 200 ns holds in all cases except when a write command register operation is followed by a read data register operation when accessing the MAP coefficient RAM. This operation requires a minimum recovery time of 450 ns. 2. Successive reads of the D-Channel Receive Buffer require a minimum cycle time (t RLRH + tRHRL) of 480 ns. 3. Read access time is measured from the falling edge of CS or the falling edge of RD, whichever occurs last. 4. CS may go Low before either RD or WR goes Low. 5. In minimal systems, CS may be tied Low. 6. Read and write indirect register operations cannot be mixed without at least one write command register operation between them. 7. CS may go High before either RD or WR goes High. 8. If CS goes High before WR goes High, the minimum Address Hold time becomes 12 ns. 9. RD and WR pulse width, Address setup and hold, and Data setup and hold timing are measured from the points where both CS and RD or WR are Low simultaneously.
80
AM79C30A/32A Data Sheet
ADDR
tAVRL tRDCS CS
tAHRH
tAVWL tWRCS
tAHWH
tRHCH tRLRH RD/WR tRACC Read tRHDZ tFHFL Read tWLWH Write tDSWH
tWHCH tWHWL Write tDHWH
DATA
09893H-21
Figure 29.
Microprocessor Read/Write Timing
Interrupt Timing
Parameter Symbol tINTC tREC Parameter Description INT Cycle Time INT Recovery Time Min 125 500 Max Units ms ns
tINTC
INT tREC
Figure 30. INT Timing
09893H-22
AM79C30A/32A Data Sheet
81
Reset and Hookswitch Timing
Reset Timing
Parameter Symbol tRES tPHRL tF tR Parameter Description Reset Pulse Width Power Stable to Reset Low Reset Transition Fall Time Reset Transition Rise Time Min 1 1 1 20 Max Units s s ms s
Hookswitch Timing
Parameter Symbol tB t1 Parameter Description Debounce Time HSW Detected to INT Delay Min 16 0 Max 16.25 370 Units ms s
Note: Due to clock start-up times, the hookswitch Min and Max Debounce times are approximately 3 ms greater in Power-Down Mode.
4.75 V VCC
tPHRL VIH
RESET
VIL
tRES tR tF
09893H-23
Figure 31.
Reset Timing
HSW
tB INT
t1
09893H-24
Figure 32.
Hookswitch Debounce Timing
82
AM79C30A/32A Data Sheet
OSC (XTAL2) Timing
Parameter Symbol tCLCL tCH tCL tCLCH tCHCL Parameter Description Oscillator Period High Time Low Time Rise Time Fall Time Test Conditions Min 81.374 33 33 10 10 Max 81.387 Units ns ns ns ns ns
Note: Frequency = 12.288 MHz 80 ppm.
MCLK Timing
Parameter Symbol tD tRISE1 tRISE2 tFALL1 tFALL2 Parameter Description XTAL2 VCC/2 to MCLK VCC/2 Rise Time Rise Time Fall Time Fall Time 12.288 MHz 6.144 MHz 4.069 MHz 3.072 MHz 1.536 MHz 768 kHz 384 kHz 12.288 MHz 6.144 MHz 4.096 MHz 3.072 MHz 1.536 MHz 768 kHz 384 kHz Test Conditions MCLK Load < 80pF MCLK Load < 80pF 0.5 V to (VCC-0.5V) MCLK Load < 40pF 1.0 V to 3.5 V MCLK Load < 80pF (VCC-0.5V) to 0.5 V MCLK Load < 40pF 3.5 V to 1.0 V 33 73 114 155 317 643 1.294 33 73 114 155 317 1.294 Min Max 60 15 5 15 5 Units ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns s
tPWH
High Pulse Width
MCLK Load < 80pF
tPWL
Low Pulse Width
MCLK Load < 80pF
tCH VCC - 0.5 V* 0.5 V tCL
tCLCH
tCHCL
Note: *Not TTL VIH
tCLCL 09893H-25
Figure 33.
External Clock Driver (XTAL2) Timing
AM79C30A/32A Data Sheet
83
tD VCC /2 OSC VCC /2 Divide by 1 12.288 MHz
Divide by 2 6.144 MHz
Divide by 3 4.096 MHz tFALL 1,2 Divide by 4 3.072 MHz tPWL tPWH tRISE 1,2
tCLK
09893H-26
Figure 34.
OSC/MCLK Timing
SBP Mode Timing
Parameter Symbol Tp* Ta Tb* tRISE tFALL tMCSC tCHFS tCLDO tDICH tCHDZ Parameter Description SCLK High time Low time SCLK rise time SCLK fall time MCLK to SCLK @ 6.144 MHz SCLK High to frame sync SBOUT Data available SBIN set-up time SBIN hold time SBOUT/SFS Load = 80 pF 200 0 ns ns SCLK Load < 80 pF SCLK Load < 80 pF MCLK Load < 80 pF SCLK Load < 80 pF 50 50 250 250 ns ns Test Conditions Min 5.025 2.594 2.431 Max 5.392 2.615 2.777 20 20 60 Units s s s ns ns ns
Note: *The frequency of SCLK is fXTAL2 / 64. Tp and Tb are based on this SCLK frequency but include a 163-ns allowance for internal-phase lock-loop correction.
84
AM79C30A/32A Data Sheet
Ta
Tb
Tp
SCLK
SBIN or SBOUT Bd Be Bf
SFS T1
BCL/CH2STRB T1 09893H-27
Notes: 1. For PPCR2(0) = 0, SBIN data is sampled on the rising edge of SCLK; SBOUT data is changed on the falling edge of SCLK. For PPCR2(0) = 1, SBIN data is sampled on the falling edge of SCLK; SBOUT data is changed on the rising edge of SCLK. 2. T1 width is eight SCLK periods.
Figure 35.
SBP Mode Timing
MCLK (6.144 MHz) tMCSC SCLK (192 kHz)
tCHFS *SFS (8 kHz) tCLDO SBOUT tDICH SBIN tCHDZ tCLDO
tCHFS
09893H-28
Notes: 1. CH2STRB timing is identical to SFS timing but delayed by eight SCLK cycles. 2. This timing diagram reflects SCLK for PPCR2(0) = 0. For PPCR2(0) = 1, the diagram is identical except that the SCLK waveform should be inverted.
Figure 36.
SBP Mode MCLK/SCLK/SFS Timing
AM79C30A/32A Data Sheet
85
IOM-2 Master Mode Timing
Parameter Data Clock Rise/Fall Clock Period Signal SCLK SCLK Abbr tR,tF tSCL Test Condition CL = 150 pF 1.536 MHz 100 PPM 163 ns* Pulse Width Frame Sync Frame Sync Setup/Clock Frame Sync Delay/Clock Frame Sync Hold/Clock Frame Delay Data Delay/Clock Data Hold/Clock Data Setup Data Hold SCLK SFS SFS SFS SFS SFS SBOUT SBOUT SBIN SBIN tWH, tWL tR,tF tSF tFD tFH tDF tDSC tDHC tSD tHD CL = 150 pF CL = 150 pF CL = 150 pF CL = 150 pF CL = 150 pF CL = 150 pF CL = 150 pF 70 tWH + 20 50 50 0 50 -tWL tWL + 50 50 100 260 ns 50 ns ns ns ns ns ns ns ns ns 487 Min Max 50 815 Units ns ns
IOM-2 Slave Mode Timing
Parameter Data Clock Rise/Fall Clock Frequency (1/period) Signal SCLK SCLK Abbr tR,tF 1/tSCLK 1.536 MHz 100 PPM 163 ns* 30 240 60 70 20 0 130 tSCLK 100** 70 tWH + 20 50 Min Max 60 Units ns Hz
Clock Delay High/Low Pulse Width Frame Sync Rise/Fall Frame Set-up Frame Hold/Clock Frame Delay/Clock Frame Width High Frame Width Low Data Delay/Clock Data Hold/Clock Data Set-up Data Hold
BCL SCLK SFS SFS SFS SFS SFS SFS SBOUT SBOUT SBIN SBIN
tBLH, tBHL tWH, tWL tR,tF tSF tFH tFD tWFH tWFL tDSC tDHC tSD tHD
ns ns ns ns ns ns ns ns ns ns ns ns
Notes: *The +163-ns value can occur once per frame for digital phase lock loop correction. **CL = 150 pF
86
AM79C30A/32A Data Sheet
BCL
** SFS SBOUT SBIN
Bit 95
Bit 0
Bit 1
Bit 2
Detail A
Note: ** SFS width is 16 SCLK cycles + setup and hold time.
tBLH
tBHL
BCL tR tF
SCLK tFD
tWH tSCU tWL
SFS*
tDF
tSF tWFH
tFH*
tDHC SBOUT tDSC tHD Transmitter Side SBIN Receiver Side Detail A tSD
09893H-29
Note: * In Master Mode, SFS is 16 SCLK cycle + setup time + hold time in length.
Figure 37.
IOM-2 Timing
AM79C30A/32A Data Sheet
87
Switching Test Conditions
(Input)
2.4 V 2.0 V Test Points 0.45 V 0.8 V 0.8 V
09893H-30
2.0 V
Note: AC testing inputs are driven at 2.4 V for a logical 1, and 0.45 V for a logical 0. Timing measurements are made at 2.0 V and 0.8 V for a logical 1, and a logical 0, respectively.
Figure 38.
Switching Test Input/Output Waveform
Device Under Test
CL = 80 pF
CL Includes Jig Capacitance
09893H-31
Figure 39.
Switching Test Load Circuit
88
AM79C30A/32A Data Sheet
APPENDIX A
Table 1.
Gain (dB) -84.3 -78.3 -72.2 -66.2 -60.2 -54.2 -50.7 -49.3 -48.7 -48.4 -48.3 -48.2 -48.1 -48.0 -47.9 -47.6 -47.1 -46.2 -45.4 -45.0 -44.8 -44.7 -44.6 -44.5 -44.3 -43.9 -43.6 -43.5 -43.4 -43.3 -43.2 -43.0 -42.9 -42.8 -42.7 -42.6 -42.5 -42.4 -42.3 -42.2 -42.1 -30.0 MSB 87 86 8F 84 8F 91 8F 90 90 90 90 8E 90 90 90 90 90 90 8F 8F 8F 8F 90 8F 8F 8F 8F 8F 8F 90 8F 8F 8F 8F 90 8F 8F 90 8E 8F 8D 90 Hex LSB 87 87 8D 87 8B 0F 92 FB FC FD FE 91 F7 F6 F5 F4 F3 F2 A2 A3 A4 A5 F1 AC AB B1 B2 B3 B4 EB BB C1 C2 C3 EC D1 D2 ED 96 F1 91 C7
Coefficients for GX, GR, and STG Attenuators
Gain (dB) -53.0 -41.9 -41.8 -41.7 -41.6 -41.5 -41.4 -41.2 -41.1 -41.0 -40.9 -40.7 -40.4 -40.3 -40.2 -40.1 -40.0 -39.8 -39.4 -39.0 -38.8 -38.7 -38.6 -38.5 -38.4 -38.3 -37.9 -37.6 -37.4 -37.3 -37.2 -37.1 -37.0 -36.8 -36.7 -36.6 -36.5 36.4 -36.3 -36.2 -36.1 -24.1 MSB 90 90 8F 8F 90 8F 8F 8F 90 8F 8F 8F 8F 8F 90 8F 8F 8F 8E 8E 8E 8E 8D 8F 8E 8F 8E 8E 8E 8E 8E 8E 8E 8E 90 8E 8E 90 8E 8E 8C 8A Hex LSB E6 E5 53 51 E4 42 41 3D E3 33 32 31 2B 2D E2 24 23 22 A2 A3 A4 A5 92 15 AC 13 B1 B2 B3 B5 BC BB C1 C2 DC CB D1 DD E2 F1 91 91 Gain (dB) -36.0 -35.9 -35.8 -35.7 -35.6 -35.5 -35.3 -35.2 -35.1 -35.0 -34.9 -34.6 -34.4 -34.3 -34.2 -34.1 -34.0 -33.8 -33.4 -33.0 -32.8 -32.7 -32.6 -32.5 -32.4 -32.2 -31.9 -31.6 -31.4 -31.3 -31.2 -31.1 -31.0 -30.8 -30.7 -30.6 -30.5 30.4 -30.3 -30.2 -30.1 -18.3 MSB 90 90 8E 8E 90 8E 8E 8E 90 8E 8E 8E 8E 8E 90 8E 8E 8E 8D 8D 8D 8D 8D 8E 8E 8E 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D 8C 91 91 Hex LSB D6 D5 52 4B D4 42 41 3C D3 33 32 31 2B 2C D2 24 23 22 A2 A3 A4 A5 A6 15 14 13 B1 B2 B3 B4 BC BB C1 C2 C3 CB D1 D2 E1 96 0B 15
AM79C30A/32A Data Sheet
89
Table 1.
Gain (dB) -29.9 -29.8 -29.7 -29.6 -29.5 -29.4 -29.3 -29.2 -29.1 -29.0 -28.8 -28.6 -28.4 -28.3 -28.2 -28.1 -28.0 -27.7 -27.3 -27.0 -26.8 -26.7 -26.6 -26.5 -26.4 -26.2 -25.9 -25.6 -25.4 -25.3 -25.2 -25.1 -24.9 -24.8 -24.7 -24.6 -24.5 -24.4 -24.3 -24.2 -12.4 -12.3 -12.2 MSB 8D 90 8D 90 8D 8D 8D 8D 90 8D 8D 8D 8D 8D 8C 8D 8D 8D 8C 8C 8C 8C 8C 8D 8C 8D 8C 8C 8C 8C 8B 8C 8C 8C 8C 90 8C 8C 8C 90 8A A0 91 Hex
Coefficients for GX, GR, and STG Attenuators (Continued)
Gain LSB 5C C5 4A C4 43 42 3A 3B C3 33 32 2A 2B 2C A1 24 23 22 A2 A3 A4 A5 A6 15 AC 13 B1 B2 B3 B4 93 BB C1 C2 C3 BC D1 D2 E1 BE D2 05 61 (dB) -24.0 -23.9 -23.8 -23.7 -23.6 -23.5 -23.4 -23.3 -23.2 -23.1 -23.0 -22.9 -22.8 -22.6 -22.4 -22.3 -22.2 -22.1 -22.0 -21.9 -21.7 -21.3 -20.9 -20.7 -20.6 -20.5 -20.4 -20.2 -19.9 -19.5 -19.4 -19.3 -19.2 -19.1 -18.9 -18.8 -18.7 -18.6 -18.5 -18.4 -7.7 -7.6 -7.5 MSB 90 90 90 8C 90 8C 8C 8C 8C 90 8C 8C 8C 8C 8C 8C 8C 90 8C 8C 8C 8B 8B 8B 8B 8C 8B 8C 8B 8B 8B 8B 8A 8B 8B 8B 8B 91 8B 8B 92 93 93 Hex LSB B7 B6 B5 4A B4 43 42 3A 3B B3 34 33 32 31 2B 2C 2E B2 24 23 22 A2 A3 A4 A6 15 AC 13 B1 B2 B3 B4 93 BB C1 C2 C3 14 D1 D2 A3 22 23 Gain (dB) -18.2 -18.1 -18.0 -17.9 -17.8 -17.7 -17.6 -17.5 -17.4 -17.3 -17.2 -17.1 -17.0 -16.9 -16.8 -16.6 -16.3 -16.2 -16.1 -16.0 -15.9 -15.7 -15.3 -14.9 -14.7 -14.6 -14.5 -14.4 -14.2 -13.8 -13.5 -13.4 -13.3 -13.2 -13.1 -13.0 -12.9 -12.7 -12.6 -12.5 -3.6 -3.5 -3.4 MSB 8B 8A 91 91 91 8B 8B 90 8B 8B 8B 8B 90 8B 8B 8B 8B 8B 8A 8B 8B 8B 91 91 8A 8A 89 91 91 8A 8A 91 91 91 91 91 91 8A 91 91 9A 9A 9A Hex LSB E2 97 1F 1E 1D 4A 4D A4 42 41 3B 3D A3 33 32 2A 2B 2E A1 24 23 22 22 23 A4 A5 92 2D 2B B1 B2 33 34 35 3C 3B 41 C2 44 4B 22 1A 1B
90
AM79C30A/32A Data Sheet
Table 1.
Gain (dB) -12.1 -12.0 -11.9 -11.8 -11.7 -11.6 -11.5 -11.4 -11.3 -11.1 -11.0 -10.9 -10.8 -10.5 -10.3 -10.2 -10.1 -10.0 -9.9 -9.7 -9.5 -9.4 -9.3 -9.2 -9.1 -9.0 -8.9 -8.8 -8.7 -8.6 -8.5 -8.4 -8.3 -8.2 -8.1 -8.0 -7.9 -7.8 0.5 0.6 0.7 0.8 0.9 MSB 8A 08 90 91 91 91 90 91 91 91 A0 91 91 92 91 92 89 92 92 91 92 92 92 92 92 92 92 92 92 A0 92 91 A0 92 92 93 93 A0 4C 43 42 41 3B Hex
Coefficients for GX, GR, and STG Attenuators (Continued)
Gain LSB F1 11 96 DA D3 D1 94 C2 C1 BB 0B B3 B2 12 AB 14 A1 1D 1B A2 22 23 24 2C 2A 32 33 3B 42 15 F7 95 1C BB B4 12 13 21 D7 57 FE FF 6F (dB) -7.4 -7.3 -7.2 -7.1 -7.0 -6.9 -6.8 -6.7 -6.6 -6.5 -6.4 -6.3 -6.2 -6.1 -6.0 -5.9 -5.8 -5.7 -5.6 -5.5 -5.4 -5.3 -5.2 -5.1 -5.0 -4.9 -4.8 -4.7 -4.6 -4.5 -4.4 -4.3 -4.2 -4.1 -4.0 -3.9 -3.8 -3.7 4.6 4.7 4.8 4.9 5.0 MSB 93 89 93 A0 A0 94 93 A0 94 93 89 95 96 97 9F 9F 9D 9D 89 9C 9D 9C 9C 89 9B 89 9C 9B 9B 9B 9B 89 9B 9A 89 9B 9A 89 12 11 10 20 09 Hex LSB 2A B3 E7 2D 2B 13 A3 32 D7 94 D1 C7 D5 A7 54 27 74 47 4B FD 01 1B 12 3C 67 33 01 22 1C 13 12 2B 0B 77 24 02 2A 22 12 C1 96 04 93 Gain (dB) -3.3 -3.2 -3.1 -3.0 -2.9 -2.8 -2.7 -2.6 -2.5 -2.4 -2.3 -2.2 -2.1 -2.0 -1.9 -1.8 -1.7 -1.6 -1.5 -1.4 -1.3 -1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 8.7 8.8 8.9 9.0 9.1 MSB A2 A2 9A A3 A3 99 A4 A5 AF AE AC 99 AB 99 99 AA AA AA B2 A9 B3 BF BE BB C1 BB C2 CE CD CA DC DB EB 00 6A 5B 5C 4A 01 01 00 00 00 Hex LSB 67 E7 12 1C 57 BA FC FB A7 3F 5F 3C F6 2A 2B 7F 2B 21 FE AA 57 6B B7 6F FF 01 FE 3F C7 7F D7 6F E7 80 F7 E7 5F 7F 1C 14 AB AA B2
AM79C30A/32A Data Sheet
91
Table 1.
Gain (dB) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 MSB 3D 33 29 32 2B 2A 19 2B 2C 2E 24 23 23 1A 22 1A 09 1B 1A 09 1C 1B 1B 1C 1D 17 16 14 20 13 20 11 12 12 12 09 Hex
Coefficients for GX, GR, and STG Attenuators (Continued)
Gain LSB C7 57 AA FE 01 7F 2A F6 5F B7 FC D7 57 12 67 1A 22 02 77 2B 00 67 E7 FD 47 A7 B7 F5 2B E7 21 93 F7 2A 22 A1 (dB) 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8.0 8.1 8.2 8.3 8.4 8.5 8.6 MSB 11 11 0A 10 0A 0B 0A 0C 0D 00 05 10 04 03 03 03 02 01 02 02 02 02 01 01 01 01 01 01 01 01 01 01 01 01 01 01 Hex LSB 2C 22 A1 A5 93 A2 91 A1 A1 90 91 4F B7 A1 B1 77 A1 92 B1 C1 41 31 A1 A2 A3 B1 B2 C1 D1 51 3B 32 2B 23 22 1A -inf. 08 10 Gain (dB) 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 10.0 10.1 10.2 10.3 10.4 10.6 10.7 10.8 10.9 11.0 11.2 11.5 11.8 11.9 12.0 12.1 12.2 12.3 12.6 13.1 14.0 MSB 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Hex LSB BB BA CA 08 69 4A 3A 3B 32 2A 2B 23 22 1A 1B 1C 15 13 12 11 0B 10 10 05 04 03 2 01 00
Table 2.
Gain (dB) -24.1 -20.6 -19.2 MSB 99 A9 99 Hex LSB 99 99 9B
Coefficients for GER Attenuators
Hex MSB 47 DA 99 LSB 99 A9 54 Gain (dB) -6.8 -6.7 -6.6 MSB 7D 9E 6E Hex LSB C9 C7 C9
Gain (dB) -11.4 -11.3 -11.2
92
AM79C30A/32A Data Sheet
Table 2.
Gain (dB) -18.6 -18.3 -18.2 -18.1 -18.0 -17.9 -17.8 -17.5 -17.0 -16.1 -15.7 -15.1 -14.8 -14.7 -14.6 -14.5 -14.4 -14.3 -14.0 -13.8 -13.5 -13.3 -13.2 -13.1 -12.9 -12.7 -12.6 -12.5 -12.4 -12.3 -12.2 -12.1 -12.0 -11.9 -11.8 -11.7 -11.6 -11.5 -2.7 -2.6 -2.5 -2.4 -2.3 MSB C9 D9 E9 99 99 99 99 49 39 29 BA 99 DA 99 99 19 A9 59 A9 99 39 EB 99 79 B9 99 DD C9 99 EE FE 79 09 59 59 57 99 55 56 5A 7B 66 4A Hex LSB 99 99 99 9F 97 96 95 99 99 99 99 AC 99 AE AF 99 96 9A 94 BC 9A 99 CC 9B 95 CE 99 97 DF 99 99 9E 99 9E 9F 99 65 99 AC DE BD AE DF
Coefficients for GER Attenuators (Continued)
Gain (dB) -11.1 -11.0 -10.9 -10.8 -10.7 -10.5 -10.4 -10.2 -10.0 -9.8 -9.7 -9.6 -9.5 -9.4 -9.2 -9.1 -9.0 -8.9 -8.8 -8.7 -8.6 -8.5 -8.4 -8.3 -8.2 -8.1 -8.0 -7.9 -7.8 -7.7 -7.6 -7.5 -7.4 -7.3 -7.2 -7.1 -7.0 -6.9 1.4 1.5 1.6 1.7 1.8 MSB FA A9 36 9A C9 34 D9 E9 99 25 FB 79 69 BA 9A 9A CA ED 19 DA F9 79 77 FA BB 49 9B A9 FC 29 EA FD 37 39 79 6F B9 DB EC 34 C2 FD D2 Hex LSB A9 91 99 BB 92 99 92 92 72 99 A9 AB AB 95 CE CF 97 A9 9D 97 91 AF 9A 95 96 AE CE 74 B9 AB AA B9 9A BB BE B9 76 94 62 7F F5 33 E5 Gain (dB) -6.5 -6.4 -6.3 -6.2 -6.1 -6.0 -5.9 -5.8 -5.7 -5.6 -5.5 -5.4 -5.3 -5.2 -5.1 -5.0 -4.9 -4.8 -4.7 -4.6 -4.5 -4.4 -4.3 -4.2 -4.1 -4.0 -3.9 -3.8 -3.7 -3.6 -3.5 -3.4 -3.3 -3.2 -3.1 -3.0 -2.9 -2.8 5.5 5.6 5.7 5.8 5.9 MSB 69 5F 66 59 59 57 56 49 D9 55 E9 55 F9 66 E9 37 36 36 A5 92 AA 92 D3 2F 27 91 77 D4 7A 6F A7 66 7A 6D 6E A3 5F 7B CF BB BE CE DF Hex LSB CF C9 9C DE DF 9D 9D DF 74 9E 64 69 54 49 73 9F 9F 79 A7 C7 55 C5 93 F9 9F A3 29 92 BE BA B7 AB CD CA CA A3 CA BC 06 02 03 04 05
AM79C30A/32A Data Sheet
93
Table 2.
Gain (dB) -2.2 -2.1 -2.0 -1.9 -1.8 -1.7 -1.6 -1.5 -1.4 -1.3 -1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 9.6 9.7 9.8 9.9 10.0 10.1 10.2 MSB 4A 5B 47 6D 65 6B 6B 5B 5B 6C B7 67 66 4E 5D 5C 5D A1 5D 4E EA 90 67 90 90 55 D4 90 ED D4 EE D3 E3 D3 D3 EE 10 E5 E2 10 10 40 46 Hex LSB EE BF AF CB 5A CE DD CF DD CD D6 BE BF EB DC DE DD A3 DE EC 42 E7 EF F6 F5 EE E5 C3 44 F4 44 E5 F6 E4 F4 43 F6 10 20 E4 C3 A0 10
Coefficients for GER Attenuators (Continued)
Gain (dB) 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 13.8 13.9 12.2 12.3 12.4 12.5 12.6 MSB FE E2 D2 E2 F2 24 24 D2 E2 C1 C1 FC D1 C1 FD D1 16 E1 E2 EE 15 17 16 BB E1 FF 09 BC DB CB FB CC BD AD AE CC E0 E0 00 00 00 00 47 Hex LSB 62 F5 F4 E4 F4 7E 6F F3 E3 D7 E7 71 D6 F5 61 E5 6D F5 F2 41 6F 4F 4F 04 F3 31 13 05 06 04 06 06 04 02 02 04 20 20 E5 D4 E4 C3 00 Gain (dB) 6.0 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8.0 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9.0 9.1 9.2 9.3 9.4 9.5 15.6 15.7 15.8 15.9 16.1 16.6 16.9 MSB EE 09 96 09 FC AC DE BE AD AE FA CD BB CE DD DE FD EE EF E7 F6 E5 D4 20 F4 10 B5 20 E3 11 C7 10 C5 20 D6 10 0A 61 50 22 40 30 B0 Hex LSB 05 70 00 50 03 01 03 02 01 01 01 02 01 02 02 02 02 02 02 20 20 20 20 E4 20 B6 10 B2 20 F2 10 C6 10 C2 10 90 00 00 10 00 10 10 00
94
AM79C30A/32A Data Sheet
Table 2.
Gain (dB) 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11.0 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 12.0 12.1 12.2 12.3 12.4 12.5 12.6 MSB 10 10 10 10 BE BF B7 00 00 01 01 F2 00 00 00 D7 00 00 F6 00 00 00 00 47 Hex LSB D3 E3 F3 A1 00 00 00 B6 B5 D2 E2 01 C7 C6 C5 00 B3 90 00 E5 D4 E4 C3 00
Coefficients for GER Attenuators (Continued)
Gain (dB) 12.7 12.8 12.9 13.0 13.1 13.2 13.3 13.4 13.6 13.7 14.0 14.1 14.2 14.4 14.5 15.0 15.3 15.4 15.5 15.6 15.7 15.8 15.9 16.1 MSB 46 00 00 F3 00 16 15 22 14 D0 72 13 52 1B 42 0C 0D 0E 0F 0A 61 50 22 40 Hex LSB 00 B2 E3 00 A1 10 10 10 10 20 00 10 00 00 00 01 01 01 01 00 00 10 00 10 -inf. 00 08 Gain (dB) 16.6 16.9 17.5 17.8 17.9 18.0 18.1 18.2 18.3 18.6 19.1 20.0 21.6 24.1 MSB 30 B0 02 D0 E0 F0 70 60 50 40 10 02 00 00 Hex LSB 10 00 10 00 00 00 00 00 00 00 10 00 10 00
AM79C30A/32A Data Sheet
95
APPENDIX B KEY DESIGN HINTS FOR THE DSC/IDC CIRCUIT
Due to the high level of integration of the AM79C30A/ 32A DSC/IDC circuit, it is easy to overlook important design information when reading the data sheet. The following list of key design hints has been compiled to streamline the design process. A comprehensive series of ISDN application notes and tutorials is available from AMD; please contact an AMD sales office or factory for current information. * The AREF pint must be used to bias the AINA and AINB inputs. There is a datasheet parameter, Vios, which states that the analog inputs must be biased to within 5 mV of AREF. AREF is nominally 2.4 V; normal device-to-device variation will exceed the 5-mV Vios specification. If a voltage other than AREF is used, transmission performance at very low signal levels will be degraded. The recommended method of biasing the AINA and AINB inputs is to use a 15-100 Kohm resistor between the input and AREF. The signal source should be AC-coupled to the analog input. Take care that the RC formed by the biasing resistor and blocking capacitor does not distort the input signal. The AREF output must not be loaded with a capacitor since it may cause the internal buffer amplifier to become unstable. For some applications involving significant gain external to the DSC circuit, the AREF output may require a simple RC noise filter. In this case, the AREF output should be isolated from the capacitor by a resistance of greater than 1 Kohm to ensure stability. The analog gain selection value (in MMR3) should be written before the MAP is enabled. The MAP auto-zero function (MMR2) should be enabled before the MAP is enabled. The DSC/IDC circuit should be provided with decoupling capacitors, situated as close as possible to the package power leads. In general, 0.1-F ceramic capacitors are sufficient, but bulk decoupling capacitors will be required if the LS1 and LS2 loudspeaker outputs are driving a heavy load. The DSC/IDC circuit is constructed on a single substrate, and therefore the device power pins must not be from separate supplies. If there is a DC offset between the analog and digital power-supply pins, excessive current may flow through the device substrate. The LS1, LS2, EAR1, and EAR2 outputs are intended to be used differentially. Although it is possible to use only a single output, the rejection of power-supply noise and internal digital noise is improved if the outputs are used differentially. * * Observe the maximum loading specification for the Ls and EAR outputs. When used differentially, the EAr outputs must see a minimum of 540 ohms between them. Similarly, the LS outputs must see a minimum of 40 ohms. The maximum capacitive loading in either case is 100 pF. The LS and EAR outputs need not be matched to the load. The LS and EAR outputs are voltage drivers and do not assume the presence of any particular load impedance. If the maximum loading specification is met, the LS and EAR outputs will function satisfactorily. In some cases, an external resistor may be used to center the desired output volume--for instance, while driving a 150-ohm earpiece with the EAR outputs. If using an EAR or LS output in a single-ended fashion, AC-couple the pin to the load. If not, the excessive DC current will cause signal distortion. When using programmable gains and filters in the MAP, consider the dynamic range effects such as truncation error and clipping. In case of questions in any particular application, please contact the AMD applications staff for assistance. All MAP tone generators are referenced with respect to the +3-dBm0 overload voltage--that is, a 0-dB tone yields a +3-dBm0 output. Take care to avoid clipping when adding tones to signals as, for example, when generating DTMF waveforms. The RC connected to CAP1/CAP2 must be situated as close as possible to the DSC circuit package to reduce the amount of noise coupled in from other signal traces. Observe the XTAL2 frequency accuracy requirement of 12.288 MHz 80 ppm. Since crystals from different manufacturers will vary, the DSC circuit oscillator output frequency at the MCLK pin must be measured and, if necessary, the value of the crystal load capacitors should be adjusted as part of the initial design procedure. An application note of oscillator considerations is available from AMD (ISDN Systems Engineering Application Note, order #12557). If driving the XTAL2 pin with the external oscillator, it is necessary to observe the datasheet input voltage and rise/fall time requirements. Note that the XTAL2 levels are not TTL-compatible. Take care in board layout of the DSC circuit, as with any sensitive analog device. An application note of DSC circuit board layout hints is available from AMD (ISDN Systems Engineering Application Note, order #12557).
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96
AM79C30A/32A Data Sheet
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The sidetone path defaults to -18-dB attenuation. If disabling the sidetone path is desired, the sidetone block must be enabled and programmed for infinite attentuation. Consider the LIU transformers, series resistors, and IC LIU output drivers as a functional unit. Transformers that meet CCITT I.430 requirements with other transceivers are not necessarily appropriate for use with the DSC circuit, and vice versa. Interrupts should be masked when reading or writing any indirect or multibyte DSC circuit registers to prevent the possibility of an interrupt occurring and destroyed the contents of the Command Register. If the MAP and secondary tone ringer are disabled, the EAR, AREF, and LS outputs are high-impedance. If the MAP is enabled, the unselected audio output is high-impedance. The MAP should not be enabled until after the LIU has achieved synchronization. This will eliminate the possibility of audible distortion when the internal device timing is resynchronized to the S Interface.
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To make optimum use of the MAP digital signal processing chain, use digital gain (GX) for fine adjustment, and analog gain (GA) for coarse adjustment. The user must program the Secondary Tone Ringer Frequency Register (STFR) with a legal value before enabling the secondary tone ringer. In order to exit Power-Down Mode due to LIU activation, both the F7 interrupt and the DSC/IDC circuit interrupt pin must be enabled. In order to exit Power-Down Mode due to IOM-2 activation, both the IOM-2 Timing Request interrupt and the DSC/IDC circuit interrupt pin must be enabled. The MAP auto-zero function must be enabled prior to enabling the MAP. For all normal applications, the auto-zero function should always be enabled. To ensure proper operation of the filters (X and R) and gains (GX, GR, GER, STGR, and ATGR), these register blocks should not be accessed more frequently than 128-s intervals. This allows the internal buffers to the map to operate properly, since they are updated only once per frame.
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AM79C30A/32A Data Sheet
97
APPENDIX C PHYSICAL DIMENSIONS
PL 044 .685 .695 .650 .656 .042 .056 .062 .083
.685 .695 Pin 1 I.D. .650 .656 .500 REF .590 .630
.013 .021
.026 .032
.050
REF
.009 .015
.090 .120 .165 .180
SEATING PLANE
TOP VIEW
SIDE VIEW
Note: Dimensions are measured in inches.
98
AM79C30A/32A Data Sheet
PHYSICAL DIMENSIONS
PQT 44 44
1
11.80 12.20
-A-
-B-
9.80 10.20
-D-
9.80 10.20 11.80 12.20 TOP VIEW
11 - 13
0.95 1.05 0.80 BSC
1.20 MAX
1.00 REF.
0.30 0.45
11 - 13
SIDE VIEW
Note: Dimensions are measured in inches.
AM79C30A/32A Data Sheet
99
(c) 1998 Advanced Micro Devices, Inc. All rights reserved. Advanced Micro Devices, Inc. ("AMD") reserves the right to make changes in its products without notice in order to improve design or performance characteristics.
The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. AMD disclaims responsibility for any consequences resulting from the use of the information included in this publication. This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any warranty of merchantability or fitness for a particular purpose. AMD products are not authorized for use as critical components in life support devices or systems without AMD's written approval. AMD assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples) of AMD products, except as provided in AMD's Terms and Conditions of Sale for such products.
Trademarks
AMD, the AMD logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. AmMAP, Digital Subscriber Controller, DSC, and IDC are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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AM79C30A/32A Data Sheet
AMENDMENT
AM79C30A/32A
Digital Subscriber ControllerTM (DSCTM) Circuit
Table 23: Amplitude Gain Coefficients on page 27 of the AM79C30A/32A final data sheet has the following changes: The tone gain block was intended to provide amplitude steps of 2 dB with a tolerance of approximately 0.5 dB. The following additional codes can also be used: -17 dB = Hex 33 -11 dB = Hex 23 -5 dB = Hex 13 The updated Table 23 reads as follows:
Table 23. Amplitude Gain Coefficients
Gain (dB) -18 -17 -16 -14 -12 -11 -10 -8 -6 -5 -4 -2 0 Hex Code 37 33 32 31 27 23 22 21 20 13 12 11 10
Publication# 09893 Rev: H Amendment/1 Issue Date: December 1998

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